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"fpga based testing of Development/Evaluation boards"

"fpga based testing of Development/Evaluation boards"

FPGA based Heart-Beat Testing of Development/Evaluation boards

FPGAs have been widely used for Designing Logic. Its usage as a critical component in a larger development project is becoming critical by the day. Customized FPGA based Development/Evaluation boards have this become widely prevalent. A big challenge forecasted in such designs is the functionality of the board as a single unit. Failure in bring-up of peripherals, board faults like open or shorts, defective parts (parts can go bust anytime) and Signal integrity issues contribute to a Board’s non-functionality. In such scenarios, a Design block developed with logic to check basic functionalities of identified peripherals becomes highly useful before a designer proceeds with implementation of targeted application on the board. The time and effort needed to debug a board, in case the board working on is faulty, is saved. This white paper explains such a Design block. The design does not require a dedicated FPGA. The same FPGA, based on which the board is designed can be used here. It is seen that this Board-Test Design (BT Design) uses only 15% of the total Logic elements available.

Features of BT Design

BT design has been successful in testing the board having the following peripherals: I2C, UART, Temperature Sensor, Timer IC, Flash, SRAM.

The code is developed in VHDL and is implemented on Altera Cyclone FPGA. A GUI has been developed to facilitate easier testing of the Board. Using the GUI, the user can choose the peripherals to be tested and the features of each peripheral that needs testing. At the end of testing, a message is displayed stating the status of the test-run. A report is also generated at the end of each test-run. This code can be easily scaled up to test more peripherals and peripheral’s features. Target FPGA too can be based on User’s preference.

Tests done by “BT Design”

VHDL code is developed and implemented in Altera Cyclone FPGA to test the mentioned features in the following peripherals.


A principle application of I2C is to configure other peripherals on the board. In this board, I2C is used to configure Temperature Sensor and Timer IC. A successful configuration of the said peripherals confirms the functionality of I2C

Temperature Sensor

This is configured using I2C. Upon enabling the Temperature Sensor (thro SCL and SDA lines), the Output data denoting the temperature, sent on SDA line is captured. The resultant data is compared using the truth table provided in the Temperature Sensor’s DataSheet and thus the functionality is validated.

Timer IC

This peripheral is configured by I2C. The timer starts upon assertion of EVENT signal and stops on de-assertion of EVENT signal. Timer Counter register is read to determine the timer value.


Read, Write and Sector Erase functionality is validated. Control signals for FLASH (Chip Enable, Write Enable and Output Enable) are sent from FPGA. This test also validates the Address and Data lines between FLASH and FPGA. Any open or short on these lines is detected and a message stating the Address/Data line wherein Open or Short was detected is displayed.


This peripheral is validated for Read and Write functionality. Similar to FLASH, tests have been developed to detect Opens or Shorts on Address./Data lines

GUI Framework

A GUI is developed to facilitate easier testing of the Board. Since the GUI framework uses the UART peripheral, seamless GUI operation validates the UART peripheral functionality too.


The BT Design is thus helpful in evaluating the basic Board functionality. Since Board functionality is assured, the Debug cycle is considerably reduced. Hardware Debugging is largely excluded from the Debug process thereby saving useful man-hours. This Design can be scaled up by including more peripherals. Hence customization of the BT Design based on BOM of each board can be easily done.

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Last update:
‎06-26-2019 03:09 PM
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