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Icon | Title | Posts | Recent Message Time Column![]() |
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Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
| 88785 Posts | 01-30-2023 06:12 PM | |
FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
| 26930 Posts | 01-30-2023 06:10 PM | |
FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
| 23927 Posts | 01-30-2023 05:10 PM | |
Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
| 4619 Posts | 01-29-2023 11:45 PM | |
Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, DLA, Software Stack, and Reference Designs
| 2107 Posts | 01-29-2023 04:18 AM | |
Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
| 51785 Posts | 01-29-2023 10:55 PM | |
Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
| 1708 Posts | 01-30-2023 11:31 AM | |
Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
| 76947 Posts | 01-30-2023 03:13 PM | |
Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
| 2938 Posts | 01-30-2023 05:13 PM | |
Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
| 4579 Posts | 01-30-2023 08:16 AM | |
FPGA Wiki | 837 Posts | 11-03-2022 01:29 PM |
by qwitza Beginner in Programmable Devices 01-30-2023 0 7 | 0 | 7 | ||
0 | 6 | |||
by Iqf Beginner in FPGA Intellectual Property 01-30-2023 0 5 | 0 | 5 | ||
by manu-solystic Beginner in FPGA Intellectual Property 01-30-2023 0 9 | 0 | 9 | ||
by MehmetFide Novice in Programmable Devices 01-30-2023 0 6 | 0 | 6 | ||
by ndevenish New Contributor I in Intel® High Level Design 01-30-2023 0 7 | 0 | 7 | ||
by jjac705 Beginner in FPGA, SoC, And CPLD Boards And Kits 01-30-2023 0 12 | 0 | 12 | ||
0 | 11 | |||
by GeraldLi1 Beginner in Intel® Quartus® Prime Software 01-30-2023 0 2 | 0 | 2 | ||
by Aswinkrishnan Beginner in Intel® Quartus® Prime Software 01-30-2023 0 1 | 0 | 1 | ||
by FPGA70 Beginner in FPGA Intellectual Property 01-30-2023 0 5 | 0 | 5 | ||
0 | 1 | |||
0 | 11 | |||
0 | 2 | |||
by grspbr Novice in FPGA Intellectual Property 01-30-2023 0 31 | 0 | 31 |
MCDMA/PCIE max number of channels - how to get 256 physical channels by grspbr 01-30-2023 0 31 |
struct -> how to add to SignalTap ? by amildm 01-09-2023 0 25 |
Issue with updating ARIA 10 PCIe core to 20_1_1 by mwf 01-30-2023 0 21 |
For more complete information about compiler optimizations, see our Optimization Notice.