Success! Subscription added.
Success! Subscription removed.
Sorry, you must verify to complete this action. Please click the verification link in your email. You may re-send via your profile.
Icon | Title | Posts | Recent Message Time Column |
---|---|---|---|
Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
| 94883 Posts | 03-18-2024 06:39 PM | |
FPGA Intellectual Property
PCI Express*, Networking and Connectivity, Memory Interfaces, DSP IP, and Video IP
| 28716 Posts | 03-18-2024 08:07 AM | |
FPGA, SoC, And CPLD Boards And Kits
FPGA Evaluation and Development Kits
| 26975 Posts | 03-18-2024 06:13 PM | |
Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
| 4943 Posts | 03-17-2024 11:05 PM | |
Application Acceleration With FPGAs
Programmable Acceleration Cards (PACs), DCP, FPGA AI Suite, Software Stack, and Reference Designs
| 2498 Posts | 03-18-2024 01:52 AM | |
Nios® V/II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® V/II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
| 52651 Posts | 03-17-2024 08:44 PM | |
Intel® SoC FPGA Embedded Development Suite
Support for SoC FPGA Software Development, SoC FPGA HPS Architecture, HPS SoC Boot and Configuration, Operating Systems
| 2509 Posts | 03-17-2024 07:03 PM | |
Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
| 82123 Posts | 03-18-2024 06:18 PM | |
Intel® High Level Design
Support for Intel® High Level Synthesis Compiler, DSP Builder, OneAPI for Intel® FPGAs, Intel® FPGA SDK for OpenCL™
| 3488 Posts | 03-17-2024 06:09 PM | |
Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
| 5656 Posts | 03-14-2024 02:50 AM | |
FPGA Wiki
Welcome to the Intel FPGA Wiki
| 364 Posts | 11-03-2022 01:29 PM |
by SeongLim Employee in Programmable Devices 03-18-2024 0 5 | 0 | 5 | ||
2 | 2 | |||
0 | 15 | |||
0 | 1 | |||
0 | 1 | |||
by jjxichn Beginner in Intel® Quartus® Prime Software 03-18-2024 0 3 | 0 | 3 | ||
0 | 2 | |||
by Jcole New Contributor I in Programmable Devices 03-18-2024 0 4 | 0 | 4 | ||
0 | 0 | |||
by Toby__5 Beginner in Programmable Devices 03-18-2024 0 3 | 0 | 3 | ||
by greenlantern01 Novice in Programmable Devices 03-18-2024 0 16 | 0 | 16 | ||
by Steve-Mowbray-ENL New Contributor I in Programmable Devices 03-18-2024 0 6 | 0 | 6 | ||
0 | 3 | |||
by TSchu3 Beginner in FPGA, SoC, And CPLD Boards And Kits 03-18-2024 0 9 | 0 | 9 | ||
by Ravalika Beginner in FPGA, SoC, And CPLD Boards And Kits 03-18-2024 0 4 | 0 | 4 |
Agilex 7 interface with DDR4 by nelky 03-13-2024 0 25 |
Questa install not working by djmohab2 03-11-2024 0 24 |
About loading constraints by Yamada1 03-18-2024 0 15 |
Community support is provided during standard business hours (Monday to Friday 7AM - 5PM PST). Other contact methods are available here.
Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.
For more complete information about compiler optimizations, see our Optimization Notice.