Xe LP Max's Memory Hierarchy

[Viet-Duc]

Dear Support Team, 

I'm looking for an official diagram for the Gen12's memory hierarchy.

For Gen9 and Gen11, official documentations are available, such as:

https://www.intel.com/content/dam/develop/external/us/en/documents/the-architecture-of-intel-processor-graphics-gen11-r1new.pdf

Specically, I would like to confirm if Gen12 does use High Bandwidth Memory (HBM) as indicated in attached Advisor Offload's report.  This result is obtained with oneAPI Advisor 2021.3.

Regards.

[AndrewG_Intel]

Hello @Viet-Duc

Thank you for posting on the Intel® communities.

Please allow us to check further this request and we will be posting back in the thread as soon as more details are available.

Best regards,

Andrew G.

Intel Customer Support Technician

[AndrewG_Intel]

Hello Viet-Duc

Thank you for your patience in this matter.

In regards to this request, we would like to inform you that we can only comment on products that have been officially released, Gen12 currently is featured on DG1 card officially known as Intel® Iris® Xe MAX Graphics. Product Specifications are available here: https://ark.intel.com/content/www/us/en/ark/products/211013/intel-iris-xe-max-graphics-96-eu.html

Memory specifications for Intel® Iris® Xe MAX Graphics are: support for LPDDR4x - 4266 MT/s

You would need to wait for Intel® ARC to be officially released to get information about it or log in to our Resource & Design Center to obtain Confidential Documents. Please note that a Corporate Non-Disclosure Agreement (CNDA) with Intel is required to obtain access to confidential documents.

Best regards,

Andrew G.

Intel Customer Support Technician

[Viet-Duc]

Hi Andrew, 

Thanks for your answer. 

In this case, may I ask for clarification regarding the DG1's memory hierarchy ? I am not interest in the bandwidth. 

It has been one years since Iris's official launch. It is currently offered in some high-end Samsung Notebooks as well. 

In case of Gen9/11, GPU slices have access to host CPU's LLC. According to oneAPI off-loading report, LLC has been replaced with HBM. 

This is why I am confused. In the presentation material for Intel Architecture Day 2021, HBM are mentioned in two places: 

• Ponte Vecchio base tile design
• Sapphire Rapids design 

So either: 

• Xe MAX will come with its own HBM, which is similar to NVIDIA design.  
• Xe MAX will access CPU's HBM configured as LLC. This required a matching Sapphire Rapids in tandem. 

 Could you please comment on this issue ? Which is correct understanding of Xe-MAX ? 

[AndrewG_Intel]

Hello Viet-Duc

Thank you for your response.

Sure, please kindly allow us to review these inquiries further. We will be posting back in the thread when more information is available.

Best regards,

Andrew G.

Intel Customer Support Technician

[AndrewG_Intel · Accepted solution]

Hello Viet-Duc

In regards to your inquiries, neither Ponte Vecchio nor Sapphire Rapids has been officially released yet, thus we can't comment on those.

DG1 only supports up to 4 channels of LPDDR4x memory and HBM is not supported. The same goes for the TGL platform (only DDR4/LPDDR4X).

If you are interested in developing a platform with Gen12 Graphics and unreleased products then our best recommendation is to sign up to our Resource & Documentation Center (a CNDA will be required). Otherwise, you should approach an Intel® Authorized Distributor for platform integration assistance.

Having said that, we will proceed to close this request now. Thank you for your understanding.

Best regards,

Andrew G.

Intel Customer Support Technician

[Viet-Duc]

Hi Andrew,

Thanks for the answers.

I am okay with closing this request since every thing is clear.

Regards.

[AndrewG_Intel]

Hello Viet-Duc

You are very welcome and thank you for your response. It has been a pleasure to assist you.

Best regards,

Andrew G.

Intel Customer Support Technician