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Which is the correct way to use the /Qax flag if I want to use SSE2,SSE3,SSSE3,SSE4.1,SSE4.2 and AVX?
This way:
/QaxSSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX
or this way:
/QaxAVX
Or is there no difference?
This way:
/QaxSSE2,SSE3,SSSE3,SSE4.1,SSE4.2,AVX
or this way:
/QaxAVX
Or is there no difference?
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/QaxAVX should generate code optimized for SSE2 and AVX-256, using 2 separate code paths where the compiler sees an advantage in it.
If you ask for the 6 different optimizations, the compiler would probably choose at most 3 of them, ideally skipping those which don't have any advantage over another, function by function. So, it's just possible the compiler may choose the same 1 or 2 paths either way. If too many are implemented, you would likely lose more from increased code size than you gain on any individual architecture.
If you never intend to run on a CPU which doesn't support SSE3, you could set
/QaxAVX /arch:SSE3 in order to optimize with just those 2 instruction sets, and support non-Intel CPUs which have SSE3.
You could check which of your files can see an advantage from the newer instruction sets and avoid requesting newer code unnecessarily. In my experience, SSE4.2 rarely shows any advantage.
If you ask for the 6 different optimizations, the compiler would probably choose at most 3 of them, ideally skipping those which don't have any advantage over another, function by function. So, it's just possible the compiler may choose the same 1 or 2 paths either way. If too many are implemented, you would likely lose more from increased code size than you gain on any individual architecture.
If you never intend to run on a CPU which doesn't support SSE3, you could set
/QaxAVX /arch:SSE3 in order to optimize with just those 2 instruction sets, and support non-Intel CPUs which have SSE3.
You could check which of your files can see an advantage from the newer instruction sets and avoid requesting newer code unnecessarily. In my experience, SSE4.2 rarely shows any advantage.
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/QaxAVX should generate code optimized for SSE2 and AVX-256, using 2 separate code paths where the compiler sees an advantage in it.
If you ask for the 6 different optimizations, the compiler would probably choose at most 3 of them, ideally skipping those which don't have any advantage over another, function by function. So, it's just possible the compiler may choose the same 1 or 2 paths either way. If too many are implemented, you would likely lose more from increased code size than you gain on any individual architecture.
If you never intend to run on a CPU which doesn't support SSE3, you could set
/QaxAVX /arch:SSE3 in order to optimize with just those 2 instruction sets, and support non-Intel CPUs which have SSE3.
You could check which of your files can see an advantage from the newer instruction sets and avoid requesting newer code unnecessarily. In my experience, SSE4.2 rarely shows any advantage.
If you ask for the 6 different optimizations, the compiler would probably choose at most 3 of them, ideally skipping those which don't have any advantage over another, function by function. So, it's just possible the compiler may choose the same 1 or 2 paths either way. If too many are implemented, you would likely lose more from increased code size than you gain on any individual architecture.
If you never intend to run on a CPU which doesn't support SSE3, you could set
/QaxAVX /arch:SSE3 in order to optimize with just those 2 instruction sets, and support non-Intel CPUs which have SSE3.
You could check which of your files can see an advantage from the newer instruction sets and avoid requesting newer code unnecessarily. In my experience, SSE4.2 rarely shows any advantage.
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