(I'm working on Windows)
The makefile I've inherited, for gcc, compiles various components of the project in place in different subdirectories. I can't figure out how to make icl put the object file in the same place as the source file (except by explicitly specifying the diirectory).
icl -c foo\\bar.c -Fofoo\\
but I don't know how to write the general rule in the makefile, to replace the gcc version:
$(CC) $(CFLAGS) $< -o $@
Do you mean you want a .o file rather than .obj? The only way I know of is to rename it in the Makefile rule.
A .c.obj rule should work fine, with appropriate settings for CC and CFLAGS, if you have added .obj to the .SUFFIXES rule.
If you are using a proprietary Windows-specific make, the answer will depend on the specific make you have chosen. I would suggest gnu make, if you are trying to modify a gnu makefile.
No, I don't mean I want .o object files. I just copied the lines from the original makefile verbatim. I have been using
$(CC) $(CFLAGS) $<
which puts the object files in the working directory. I haven't added a .SUFFIXES rule (the original makefile doesn't have one). Will that make a difference? If so, what should it look like?
Are you using Cygwin or something similar that provides you with unix utilities like dirname? If so you could do something like
$(CC) $(CFLAGS) $< -Fo`dirname $<`\
but I think cygwin will give you forward slashes which might confuse things.