How is AVX512 instruction counted when calculating IPC?

[oleotiger]

In HPC running, many sse instructions are used. Single instructions and datas are packed into a instruction with multiple datas.

If a AVX512 instruction is retired in a cycle, what is the IPC on this core?

IPC=1?

Is the complex instruction counted just as 1? or 2 or 3?

[NoorjahanSk_Intel]

Hi,

Thanks for reaching out to us.

>> IPC=1?
Generally the value of IPC for HPC applications is 1 but it varies according to the type of application domain as there are some parametrs which effects the IPC value.
Please refer the following link for more details
https://software.intel.com/content/www/us/en/develop/documentation/vtune-help/top/reference/cpu-metrics-reference/ipc.html

We are trying to fetch the information from internal team. We will get back to you soon.

Thanks & Regards

Noorjahan

[NoorjahanSk_Intel]

Hi,

Could you please let us know what you wanted to achieve by getting this IPC value >> If a AVX512 instruction is retired in a cycle, what is the IPC on this core?

and also do let us know which tool you are using to get the IPC value.

Could you please give us  more details about your issue , so that it will help us  better to answer your query.

Thanks & Regards

Noorjahan.

[oleotiger]

I wanna to evalute the performance of a HPC app with IPC.

IPC is got with perf and pcm.

I just wonder how AVX512 is counted in PMU registers. 

If a general app has a high ipc, we can say that it runs efficiently.

Just regarding IPC, can it evalute the performance of a HPC app compared with a general app?

Will the behavior (instructions packed as AVX512) results in low IPC?

[Bernard]

---

@oleotiger wrote:

In HPC running, many sse instructions are used. Single instructions and datas are packed into a instruction with multiple datas.

If a AVX512 instruction is retired in a cycle, what is the IPC on this core?

IPC=1?

Is the complex instruction counted just as 1? or 2 or 3?

---

AVX512 instructions (depends on their type) are decomposed into single micro-instruction when  all operands are registers. When one of the operands is a memory address then such instruction will be decomposed (decoded) into 2 micro-instructions (uops) in regards to fused/unfused domain, anyway it shall be looked per specific instruction type as the decoding into uops varies. At the retirement stage there is a count of retiring instructions and not their uop representation.

An IPC metric sometimes may be a crude approximation especially for the interspersed computational/not-computational code or base-blocks.

[jimdempseyatthecove]

MMX/SSE/AVX/AVX2/AVX512 are SIMD instructions: Single Instruction Multiple Data

There is a distinction to be made between:

Instructions per clock

   and

operations per data item per clock

This can also be thought of as a difference between:

Floating Point instructions per second (regardless of vector presence or width)

  and

Floating point ops*vector width per second (Flops)

Jim Dempsey

[NoorjahanSk_Intel]

Hi,

>>Is the complex instruction counted just as 1? or 2 or 3?

Could you please elaborate on complex instructions in detail with an example that helps us to get more insights to resolve your issue

Usually, one AVX instruction is  equal to IPC value of 1 (IPC=1)

As it is SIMD instruction, it will be retired as a complete single instruction.

For more details you can refer to the below link:

https://software.intel.com/content/dam/develop/external/us/en/documents-tps/64-ia-32-architectures-optimization-manual.pdf

Thanks & Regards

Noorjahan

[NoorjahanSk_Intel]

Hi,

Reminder:

 Has the information provided above helped? If yes then could you please confirm whether we can close this thread from our end? If not please provide the above-requested details.

Thanks & Regards

Noorjahan.

[NoorjahanSk_Intel]

Hi,

We have not heard back from you, so we will close this inquiry assuming your issue has been resolved. If you need further assistance, please post a new question.

Thanks & Regards

Noorjahan