I 've been working on a talk about cache effects. My main document is "What every programmer should know about memory". I've been working on small benchmark that shows the different level of caches : walking an array of objects in a linear/randomized order. The 3 levels of cache are quite obvious when walking in a randomized order, and I measure about one cache line every 300 clock cycles on a Xeon 2xxx once the program has to go to main memory.
The paper "What every programmer should know about memory" states that this is more that the main memory latency because the hardware needs to translate virtual addresses to physical addresses and you might be slow down by the TLB.
What surprises me is that some people claim some very accurate numbers for L1/L2/L3/main memory access. So here are my questions ?
- On what does the memory latency depend upon ? CPU / Mother board / RAM
- Does Intel give measurement for memory latency ?
- How do people measure this latency ? If the author of "What every programmer should know about memory" claims that 300 cycles is more than the memory latency, he must have a way of knowing this latency. Unfortunately, he does not give any hint on how to get/measure it.