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I recently downloaded the intel c++ compiler 8.0 evaluation version and used it to compile my program in vs.net 2003. I found the releaseconfiguration did not produce the correct results. The debug configuration of the intel compiler and both the debug and release configurations of the vs.net compiler produced the expected results. As I tracked down the part of the code that caused the problem, it seemed to be a problem of the compiler.
I created a very simple program.
int _tmain(int argc, _TCHAR* argv[])
{
double x =NaN;
double y = 1.0;
if (x < y)
cout << x << " is less than " << y << endl;
else
cout << x << " is not less than " << y << endl;
return 0;
}
x isa quietNaN (Not-a-Number). The value of the expression "NaN < 1.0" should be false.
If it is compiled correctly, the program should output "1.#QNAN is not less than 1".
But when I turned on the "/O2" optimization option in the DEBUG configuration, the compiled program output "1.#QNAN is less than 1".
Any floating point comparisoninstruction involving NaN followed by "fnstsw ax" and "sahf" sets the C, Z, and P flags. The P flag indicates that an operand is NaN.
But the assembly code in the disassembly window showed that the parity flagwas not checked in the optimized code. In the unoptimized code, the parity flag was checked explicitly.
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Hi,
I'm not familiar on all of the details on IA-32 FP execution. If nobody on the forum is able to help, I'dsuggest opening an issue at http://premier.intel.com ? When you download the evaluation version of the compiler, you are also able to evaluate our support.You should've recieved information on how to register for support when you got the license key, or you can look at the product release notes.
regards,
John
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I always got a HTTP 403 error after I logged into the premier support site. Why?
Message Edited by shuying on 02-11-2004 02:53 PM
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There is a way around this issue.
You can add the /Qprec option:
/Qprec improve floating-point precision (speed impact less than /Op)
It will alter the comparison sequence from:
fcom
fnstsw ax
sahf
jae $B1$3
fnstsw ax
sahf
jae $B1$3
to
fcomp st(2)
fnstsw ax
sahf
jp $B1$3
jb $B1$2
jmp $B1$3
fnstsw ax
sahf
jp $B1$3
jb $B1$2
jmp $B1$3
at some performance cost. Itshould treat NaN as unordered and do what you want.
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