Intel® C++ Compiler
Support and discussions for creating C++ code that runs on platforms based on Intel® processors.
7701 Discussions

Prescott/intrinsics and compiler

dessa
Beginner
307 Views
I'm trying to implement/test SSE3 versions of some functions, and it seems that Intel Compiler doesn't
understands new Prescott intrinsics, like:
_mm_lddq_si128()

Does anybody knows workaround for this?

Thanks,
Alex
0 Kudos
5 Replies
TimP
Black Belt
307 Views

Message Edited by tim18 on 08-25-2004 06:16 AM

dessa
Beginner
307 Views
I'm using Intel C/C++ 7.1 on Prescott system. Is 8.0 beta version of the compiler?

Alex
TimP
Black Belt
307 Views

Message Edited by tim18 on 08-25-2004 06:09 AM

Anna_N_
Beginner
307 Views
tcprince: Thanks for answering half-year-old questions.

Question 1. Is "SSE3" name official or just world-wide-used? Last time I checked manuals, it was still "PNI"...

Q2. There are intrinsics for integer rotates (ROL/ROR) in ICC, are bitscan (BSF/BSR) intrinsics planned?

Q3. Now that intrinsics and opcodes are known to the public, can you tell if MOVDDUP, MOVSHDUP and MOVSLDUP use FP_MOVE, MMX_MISC or MMX_SHFT execution units (or which of their Prescott equivalents)? A combination of the above?

Q4. Is there an oficial reason for MOVDDUP, MOVSHDUP and MOVSLDUP being typed, i.e. that they "should only be used with" SSE2 DP FP or SSE SP FP computations, respectively? Does that mean they use FTZ/DAZ or similar mechanism on input data?

Q5. Is it possible that a future Intel Compiler for Itanium (IPF/IA64) will be able to accept SSE2 and PNI intrinsics?
For __m128d that should be easy (just two registers, shuffles become moves etc.), for __m128i maybe a little harder (two 64bit registers, both in parallel mode; arithmetic the same, only shuffles/shifts somewhat more complicated)...
If SSE2/PNI intrinsics were available on Itanium, porting of many IA32-optimized (P4-optimized) kernels would be much faster.

Best regards,

Anna
TimP
Black Belt
307 Views

Message Edited by tim18 on 08-25-2004 06:09 AM

Reply