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I'm a bit new to doing anything complictaed when compiling anything, so this might be me just being a bit silly.
When compiling a c++ program, I need to surpress linking and call the object something other then the c++ scripts filename .To do this, I'm using -o option to rename the object file and -c to stop linking. The actual program I'm trying to do it with is a little large and complicated, but I've managed to replicate the problem I'm having with a simple makefile:
[plain]Cxx = icl yayandwow: wow.o wow.o : simples.cpp $(Cxx) -o $@ -c $^ [/plain]
when I do make yayandwow, it makes simples.obj when I'm hoping it would make wow.o (or maybe wow.obj, but definatly a wow.something). The compilation itself is fine, the object file just called the wrong name.
I'm using Intel C++ Compiler Professional for applications running on IA-32, Version 11.1.067. I'm on a windows 11 OS. I've tried it on DOS and through cygwin. It worked fine on my previous machine using an Intel c compiler (I forget with version) and a Linux OS.
incidently, I'm having the same problem fortran and ifort, but I notcied it first with c++ so thats wjy I stuck it here.
Any ideas?
Thanks in advance
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The compiler option to specify a non-standard object file name for the Windows version of the Intel compilers is the /Fo option.
You may also need to supply or modify the .c.o, .f.o, .f90.o. cpp.o, etc., implicit rules in your makefile, and possibly specify SUFFIXES rules, all depending which version of make you use.
The alternative is to accept the Windows default .obj extension, and provide implicit rules for .c.obj, etc.
You may also need to supply or modify the .c.o, .f.o, .f90.o. cpp.o, etc., implicit rules in your makefile, and possibly specify SUFFIXES rules, all depending which version of make you use.
The alternative is to accept the Windows default .obj extension, and provide implicit rules for .c.obj, etc.
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As mecej4 indicated, VS compatible compilers don't implement a -o option, using -Fo in a similar role.
A frequently used Windows posix Makefile idiom accepts the default .obj naming, then renames it as required, e.g.
CC = ICL
CFLAGS = -Qansi-alias -Qprec-div -Qprec-sqrt -Qstd=c99
.SUFFIXES: .obj
.....
.c.o:
$(CC) -c $(CFLAGS) $*.c
mv $*.obj $*.o
In my personal experience, the main drawback is in the cases where make -j is broken because of conflicts in the renaming phase (likely to happen on account of multiple .exe or .pdb having the same default name).
The main reason for renaming .obj to .o is to improve commonality among OS in the remainder of a Makefile.
Needless to say, whatever you do with Makefile on Windows will arouse ire in many quarters.
A frequently used Windows posix Makefile idiom accepts the default .obj naming, then renames it as required, e.g.
CC = ICL
CFLAGS = -Qansi-alias -Qprec-div -Qprec-sqrt -Qstd=c99
.SUFFIXES: .obj
.....
.c.o:
In my personal experience, the main drawback is in the cases where make -j is broken because of conflicts in the renaming phase (likely to happen on account of multiple .exe or .pdb having the same default name).
The main reason for renaming .obj to .o is to improve commonality among OS in the remainder of a Makefile.
Needless to say, whatever you do with Makefile on Windows will arouse ire in many quarters.
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This seems an issue with make and not of Intel compiler.

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