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What doesn't it mean? "Enable non-temporal store using #pragma vector nontemporal"

mikeitexpert
New Contributor II
295 Views

Dear Experts,

I have been using Intel Advisor for quite some time recently and I really love it.

 

I came across the below recommendation quite many times and but I have a hard time understanding it.

In particular I can't make sense of :

". The nontemporal clause instructs the compiler to use non-temporal (that is, streaming) stores on systems based on all supported architectures, unless specified otherwise; optionally takes a comma-separated list of variables."

 

To me streaming means using SIMD which I have applied to the loop. I don't understand why it is still showing up in the Recommendations tab. Unless, non-temporal means sth different. I have read the Compiler User Guide for that matter, still not getting what I can do better. 

 

I appreciate your valuable comments.

Mike

 

mikeitexpert_0-1622633385884.png

 

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1 Solution
jimdempseyatthecove
Black Belt
286 Views

Streaming stores does not mean SIMD (SIMD does not mean streaming stores).

 

Streaming stores means (the following statement in total)

You are writing a sequence of data (either by scalar or SIMD instructions) and this sequence of data is not going to be referenced shortly thereafter. Therefore, you desire to NOT have the data being written to be evicting L1 and/or L2 and/or L2 cache lines. Instead, your preference is to write directly to memory without storing results additionally in cache.

References:

https://software.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-...

https://software.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-...

 

Jim Dempsey

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3 Replies
jimdempseyatthecove
Black Belt
287 Views

Streaming stores does not mean SIMD (SIMD does not mean streaming stores).

 

Streaming stores means (the following statement in total)

You are writing a sequence of data (either by scalar or SIMD instructions) and this sequence of data is not going to be referenced shortly thereafter. Therefore, you desire to NOT have the data being written to be evicting L1 and/or L2 and/or L2 cache lines. Instead, your preference is to write directly to memory without storing results additionally in cache.

References:

https://software.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-...

https://software.intel.com/content/www/us/en/develop/documentation/cpp-compiler-developer-guide-and-...

 

Jim Dempsey

mikeitexpert
New Contributor II
250 Views
VidyalathaB_Intel
Moderator
238 Views

Hi,

>>thank you much appreciate it.

Thanks for the confirmation!

As your issue has been resolved, we will no longer respond to this thread. 

If you require any additional assistance from Intel, please start a new thread. 

Any further interaction in this thread will be considered community only. 

Have a Good day.

Regards,

Vidya.

 

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