effective address in 16, 32 and 64 bits IA-32 and intel 64 architectures

[logicman112]

My question is how we can write effective address in 16, 32 or 64 bit modes. We know that the following is a valid effective address in 16 bit IA-32 protected:
[BX+SI]+disp8
Can we specify: [BH+SI]+disp8 as an address?

Also suppose we write a code for IA-32 protected, the following is a valid effective address:
[EAX]+disp32

But is , [AX]+disp32 a valid valid effective address? how about [AL]+disp32?

In real mode(16-bit) we have [BX]+disp8 but is "[BL]+disp8" valid?

And my last question is that how you write a valid address in 64 bit mode?

[Dmitry_K_Intel2]

I'm afraid this is not the best forum for such a question. Could you report it in compiler forum?

Regards!
Dmitry

[mecej4]

Your assembler can answer these questions for you in 'yes'/'no' fashion. For example:

[bash]~/LANG> cat > t.s
.text
movl $320,120(%ax)
~/LANG> as -32 t.s
t.s: Assembler messages:
t.s:2: Error: `120(%ax)' is not a valid base/index expression
~/LANG>
[/bash]

Another alternative is to read one of the freely available instruction set manuals for your processor.

As to your question on effective addresses in 64-bit mode: very similarly to 16 and 32 bit mode, except that addresses have to be 64 bits. For example:

orl $32832, -112(%rbp)

in contrast to the 32-bit version

orl $32832, -112(%ebp)