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hardware prefetching programmatically

roberto_g_2
New Contributor I
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We know how to perform software prefetching using C++ intrinsics.

As for hardware prefetching to improve cache performance, Chapter 8 in the document Intel 64 and IA-32 Architectures Optimization Reference Manual shows how to do that using inline asm. Following that suggestion, we could use the following inline assembly to hw prefect 512 bytes (where, alternatively, mov r9 can be replaced by vmovaps ymm0):

 

inline void Prefetch512_HW(void* address)
{
 _asm {
       mov rsi, address
       mov r9, [rsi]
       mov r9, [rsi+64]
       mov r9, [rsi+128]
       mov r9, [rsi+192]
       mov r9, [rsi+256]
       mov r9, [rsi+320]
       mov r9, [rsi+384]
       mov r9, [rsi+448]
      }
}

 

  1. Is there a lighter (faster) way to attain the same goal? Loading a byte in each mov instruction? Using some alternative instruction to mov for those addresses?
  2. Suppose that we have a large number of 4KiB virtual pages and want to improve TLB caching (page walk) of those addresses: how can we make it easy programmatically? 

Thank you

-Roberto

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PrasanthD_intel
Moderator
790 Views

Hi Roberto,


Due to some error, your query has been marked spam. But you have already raised another thread. So we are closing this thread as this became a duplicate

of the new thread - https://community.intel.com/t5/Intel-C-Compiler/hardware-prefetching-programmatically-posted-again/m-p/1188035#M37175


Regards

Prasanth


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PrasanthD_intel
Moderator
791 Views

Hi Roberto,


Due to some error, your query has been marked spam. But you have already raised another thread. So we are closing this thread as this became a duplicate

of the new thread - https://community.intel.com/t5/Intel-C-Compiler/hardware-prefetching-programmatically-posted-again/m-p/1188035#M37175


Regards

Prasanth


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roberto_g_2
New Contributor I
778 Views

Yes please, thank you Prasanth!

-Roberto

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