"error ADX is not available" when using ICC 17.0.4 on a Skylake machine

[noloader]

Hi Everyone,

I'm trying to compile a program that uses ADX. ICC version is:

$ icc --version
icc (ICC) 17.0.4 20170411

The machine is a 6th gen Core i5, so ADX is available. ADX first appeared in 5th gen Core processors.

I'm using `-march=native` which should activate AVX2, BMI2 and other goodies like ADX on this particular machine. When I attempt to compile:

$ icc -Wall -O3 -march=native test.cxx -o test.exe
test.cxx(14): error: #error directive: ADX is not available
  # error ADX is not available
    ^
...

The error is triggered by the following in test.cxx:

#if !defined(__ADX__)
# error ADX is not available
#endif

Adding `-mcpu=corei5` does not help, and adding `-madx` results in an error.

I can't find local man pages. Searching online for the options pretty much sucks. I've found the ICC(1) man page at https://software.intel.com/sites/default/files/m/d/4/1/d/8/icc.txt, but it stops at Pentium 4's. Other than that, I'm getting useless hits for "intel icc enable adx".

How do I compile a program that uses ADX under ICC?

Thank you in advance.

-----

Here are the preprocessor macros provided by ICC.

skylake:$ icc -march=core-avx2 -dM -E - </dev/null | sort
#define __amd64 1
#define __amd64__ 1
#define __ATOMIC_ACQ_REL 4
#define __ATOMIC_ACQUIRE 2
#define __ATOMIC_CONSUME 1
#define __ATOMIC_HLE_ACQUIRE 65536
#define __ATOMIC_HLE_RELEASE 131072
#define __ATOMIC_RELAXED 0
#define __ATOMIC_RELEASE 3
#define __ATOMIC_SEQ_CST 5
#define __AVX__ 1
#define __AVX2__ 1
#define __AVX_I__ 1
#define __BIGGEST_ALIGNMENT__ 64
#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
#define __CHAR16_TYPE__ unsigned short
#define __CHAR32_TYPE__ unsigned int
#define __CHAR_BIT__ 8
#define __cilk 200
#define __DATE__ "Aug 21 2017"
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#define __DBL_DIG__ 15
#define __DBL_EPSILON__ 2.2204460492503131e-16
#define __DBL_HAS_DENORM__ 1
#define __DBL_HAS_INFINITY__ 1
#define __DBL_HAS_QUIET_NAN__ 1
#define __DBL_MANT_DIG__ 53
#define __DBL_MAX_10_EXP__ 308
#define __DBL_MAX__ 1.7976931348623157e+308
#define __DBL_MAX_EXP__ 1024
#define __DBL_MIN_10_EXP__ -307
#define __DBL_MIN__ 2.2250738585072014e-308
#define __DBL_MIN_EXP__ -1021
#define __DEC128_EPSILON__ 1E-33DL
#define __DEC128_MANT_DIG__ 34
#define __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL
#define __DEC128_MAX_EXP__ 6145
#define __DEC128_MIN__ 1E-6143DL
#define __DEC128_MIN_EXP__ -6142
#define __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL
#define __DEC32_EPSILON__ 1E-6DF
#define __DEC32_MANT_DIG__ 7
#define __DEC32_MAX__ 9.999999E96DF
#define __DEC32_MAX_EXP__ 97
#define __DEC32_MIN__ 1E-95DF
#define __DEC32_MIN_EXP__ -94
#define __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF
#define __DEC64_EPSILON__ 1E-15DD
#define __DEC64_MANT_DIG__ 16
#define __DEC64_MAX__ 9.999999999999999E384DD
#define __DEC64_MAX_EXP__ 385
#define __DEC64_MIN__ 1E-383DD
#define __DEC64_MIN_EXP__ -382
#define __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD
#define __DEC_EVAL_METHOD__ 2
#define __DECIMAL_BID_FORMAT__ 1
#define __DECIMAL_DIG__ 21
#define __EDG__ 1
#define __EDG_PTRDIFF_TYPE__ long
#define __EDG_SIZE_TYPE__ unsigned long
#define __EDG_VERSION__ 411
#define __ELF__ 1
#define __FINITE_MATH_ONLY__ 0
#define __FLOAT_WORD_ORDER__ __ORDER_LITTLE_ENDIAN__
#define __FLT_DECIMAL_DIG__ 9
#define __FLT_DENORM_MIN__ 1.40129846e-45F
#define __FLT_DIG__ 6
#define __FLT_EPSILON__ 1.19209290e-7F
#define __FLT_HAS_DENORM__ 1
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#define __FLT_MAX__ 3.40282347e+38F
#define __FLT_MAX_EXP__ 128
#define __FLT_MIN_10_EXP__ -37
#define __FLT_MIN__ 1.17549435e-38F
#define __FLT_MIN_EXP__ -125
#define __FLT_RADIX__ 2
#define __FMA__ 1
#define __GCC_ATOMIC_BOOL_LOCK_FREE 2
#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
#define __GCC_ATOMIC_INT_LOCK_FREE 2
#define __GCC_ATOMIC_LLONG_LOCK_FREE 2
#define __GCC_ATOMIC_LONG_LOCK_FREE 2
#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
#define _GLIBCXX_NO_BUILTIN_HAS_UNIQ_OBJ_REP 1
#define _GLIBCXX_NO_BUILTIN_LAUNDER 1
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#define __GNUC_MINOR__ 0
#define __GNUC_PATCHLEVEL__ 0
#define __GNUC_STDC_INLINE__ 1
#define __gnu_linux__ 1
#define __GXX_ABI_VERSION 1010
#define __ICC 1700
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#define __INTEL_COMPILER_BUILD_DATE 20170411
#define __INTEL_COMPILER_UPDATE 4
#define __INTEL_OFFLOAD 1
#define __INTEL_RTTI__ 1
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#define __INT_FAST64_TYPE__ long
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#define __SSE_MATH__ 1
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#define __STDC_DEC_FP__ 200704L
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#define __TIME__ "09:48:47"
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#define __UINT_FAST16_TYPE__ unsigned long
#define __UINT_FAST32_MAX__ 18446744073709551615UL
#define __UINT_FAST32_TYPE__ unsigned long
#define __UINT_FAST64_MAX__ 18446744073709551615UL
#define __UINT_FAST64_TYPE__ unsigned long
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#define __UINT_FAST8_TYPE__ unsigned char
#define __UINT_LEAST16_MAX__ 65535
#define __UINT_LEAST16_TYPE__ unsigned short
#define __UINT_LEAST32_MAX__ 4294967295U
#define __UINT_LEAST32_TYPE__ unsigned int
#define __UINT_LEAST64_MAX__ 18446744073709551615UL
#define __UINT_LEAST64_TYPE__ unsigned long
#define __UINT_LEAST8_MAX__ 255
#define __UINT_LEAST8_TYPE__ unsigned char
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#define __WCHAR_TYPE__ int
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#define __WINT_MIN__ 0U
#define __WINT_TYPE__ unsigned int
#define __x86_64 1
#define __x86_64__ 1
skylake:$

[Viet_H_Intel]

Can you use intrinsics? _addcarryx_u32/addcarryx_u64

Regards,

Viet Hoang

[Melanie_B_Intel · Accepted solution]

In the gcc compiler, you may need to add the "-madx" option which also enables the __ADX__ target specific macro. But that's not necessary on the Intel compiler and icc doesn't activate the target macro's in the same way that gcc does.

gcc -c -madx -dM -E test.c | grep ADX
#define __ADX__ 1

icc -c -madx -dM -E test.c | grep ADX
icc: command line warning #10159: invalid argument for option '-m'

See, without the -madx argument, gcc doesn't create the macro:

  gcc -c -dM -E test.c | grep ADX

I wrote a small test case to confirm that the adx instructions are being generated

 icc -c -S test.c 
 grep adcx test.s
        adcx      %rdx, %rsi                                    #5.9
 cat test.c

unsigned char fu(
  unsigned char c_in, unsigned __int64 a, unsigned __int64 b, unsigned __int64 * out)
{
 return _addcarryx_u64 (c_in, a, b, out);
}

[noloader]

Thanks Viet Hoang and Melanie Blower. Please forgive my ignorance...

When using ICC, how do we know when a user wants a particular target feature? In the case of ADX, is it lumped into AVX2 (such that __AVX2__ signals it)?

If not, what happens when I want to build for a minimum target like AVX? How do I know _not_ to enable AVX2 and BMI2, and ADX in this case?

And I guess the other question is, why doesn't ICC define __ADX__ when in GCC mode? Its claiming to be GCC with __GNUC__ and friends.

[Melanie_B_Intel]

I've created CMPLRS-6758 in our internal bugs database to request for the compiler to recognize -madx, and add the target macro too. Thanks for pointing this out. 

The compiler does accept many of gcc's -m options and the target macro symbols defined vary depending on that option, for example I saw these differences,

using icc -c
< -D__i686__
< -D__pentiumpro
using -c -mavx
> -D__SSE3__
> -D__SSSE3__
> -D__SSE4_1__
> -D__SSE4_2__
> -D__AVX__

I think if you actually have a call to a builtin intrinsic, the compiler doesn't check if it's supported (w.r.t. the -m option that you chose) it just assumes you know what you're doing.