The descriptor's addresses mechanism is based on GDT.My unclear problem is : 1.Since GDT must be present all time in memory , it's area of memory which reside in is in RAM memory or in Cache L1 memory which i think it must be a content adressable memory.
My presumtion : if it is is in RAM every access must include a read from RAM, do something, write-back in RAM the descriptor
If it is in L1 cache CAM memory it seem to be more simple ,since CAMis hit or no by a descriptor adress
