I need help in developing logic to solve my problem. I am developing ultrasonic sensor which operates in single or dual mode. In dual mode it requires synchronization signal. Below image is part of the design where I need to take decision on input SYNC signal. When the SYNC signal is connected to CPLD, it gives 3.9 KHz as input and when SYNC signal is disconnected the same pin is pulled high to Vcc (i. e. logic 1). So I need a logic (schematic or VHDL code) which will give me output as per the truth table given below. I tried different logic circuit using gates and FF but not succeed. I tried the VHDL coding also, but its giving error. Please help.
Thanks for your reply. I realized my mistake after posting the question. Now I am unable to delete the post due to 'administrator has disabled cascaded deletions of feed post'. I request to delete the post.