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initialization time of Block ram and highspeed IO after power on FPGA

lambert_yu
Beginner
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Hi all,

   Now I am debuging one strange problem: For one project, after poweron , the current of core changes 2A->3A-5A, 3A->5A needs 3~4 ms; after I add another module into previous project, the current of core changes 2A->3A->5A, 3A->5A needs 14~16ms; I check that for the added module, it includes large block ram and highspeed IO, other part is general Flip-Flops, so I want to know the initialization time of large block ram (no initial data) and highspeed IO,  does their initialization affect the current switching time, this is one key problem for me, could someone give me some help.

 

Brs,

Lambert

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