FPGA bitstream generation error (qsys generate failed) on DevCloud

[YuanM]

Hi,

I am trying the latest OneAPI tutorial example: https://github.com/oneapi-src/oneAPI-samples/tree/master/DirectProgramming/C%2B%2BSYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming

For bitstream generation, I am following the steps:

qsub -I -l nodes=1:fpga_runtime:ppn=2 -d .
mkdir build & cd build
cmake ..
make fpga

 and got the following error:

[ 50%] Building CXX object src/CMakeFiles/simple_host_streaming.fpga.dir/simple_host_streaming.cpp.o
[100%] Linking CXX executable ../simple_host_streaming.fpga
warning: -reuse-exe file '/home/u186670/oneapi_may15_23/oneAPI-samples/DirectProgramming/C++SYCL_FPGA/Tutorials/DesignPatterns/simple_host_streaming/build/simple_host_streaming.fpga' not found; ignored
aoc: Compiling for FPGA. This process may take several hours to complete.  Prior to performing this compile, be sure to check the reports to ensure the design will meet your performance targets.  If the reports indicate performance targets are not being met, code edits may be required.  Please refer to the oneAPI FPGA Optimization Guide for information on performance tuning applications for FPGAs.
Error: qsys generate failed!!

llvm-foreach: 
icpx: error: fpga compiler command failed with exit code 1 (use -v to see invocation)
src/CMakeFiles/simple_host_streaming.fpga.dir/build.make:94: recipe for target 'simple_host_streaming.fpga' failed
make[3]: *** [simple_host_streaming.fpga] Error 1
CMakeFiles/Makefile2:126: recipe for target 'src/CMakeFiles/simple_host_streaming.fpga.dir/all' failed
make[2]: *** [src/CMakeFiles/simple_host_streaming.fpga.dir/all] Error 2
CMakeFiles/Makefile2:101: recipe for target 'src/CMakeFiles/fpga.dir/rule' failed
make[1]: *** [src/CMakeFiles/fpga.dir/rule] Error 2
Makefile:118: recipe for target 'fpga' failed
make: *** [fpga] Error 2

Using an FPGA-compile-node leads to a similar error. 

I am working on a project which also uses pipes for host-device and on-chip data streaming, and I use the CMakeLists in this example for compiling the bitstream but experience a similar error as above. Could you please advise what is the problem and how I can work around this using the GitHub example?

[AlekhyaV_Intel]

Hi,

Thank you for posting in Intel Communities. We were able to reproduce this issue. We have contacted the admin team and will get back to you soon with an update.

Regards,

Alekhya

[YuanM]

Hi Alekhya,

I wonder if there is any update to the issue?

Thanks.

[AlekhyaV_Intel]

Hi,

We have escalated this issue to the respective team and they're working on it. As of now, we did not any update in this. We will get back to you soon.

Regards,

Alekhya

[Christoph9]

Hey,

I also have the problem. quartus_sh_compile.log show the following errors:

a 10" --part=Unknown
2023.06.01.09:10:36 Warning: vector_add_fpga_di_inst: Invalid device family name in input file: Agilex
2023.06.01.09:10:36 Warning: vector_add_fpga_di_inst: Invalid device name in input file: AGFB014R24A2E2VR0
2023.06.01.09:10:36 Error: top_vector_add_fpga_di: Component vector_add_fpga_di_inst does not support selected device family Arria 10
2023.06.01.09:10:36 Error: qsys-generate failed with exit code 3: 1 Error, 2 Warnings
2023.06.01.09:10:36 Info: Finished: Create HDL design files for synthesis
2023.06.01.09:10:36 Info: Starting: IP-XACT
2023.06.01.09:10:36 Info: qsys-generate /home/u153009/tmp/vector_add-67382f-7fb977/top_vector_add_fpga_di.ip --synthesis=VERILOG --ipxact --output-directory=/home/u153009/tmp/vector_add-67382f-7fb977/top_vector_add_fpga_di --family="Arria 10" --part=Unknown
2023.06.01.09:10:36 Info: Finished: IP-XACT

So my guess would be the Agilex BSP not being properly installed.

Are there any updates to this? I have a bad Déjà-vu when thinking on the last FPGA compile issue (https://community.intel.com/t5/Intel-DevCloud/FPGA-Builds-Broken-on-DevCloud/m-p/1439447#M6881) which was unfixed for more than 3 months. And now this issue is again persisting for weeks.

I know that Intel Devcloud is a free service, and I am very happy that it exists. However, the service being not usable for >4 month of a year - which is a horrendous uptime for an online service btw - makes it kind of obsolete and just bad press for Intel beween developers.

Remember multiple people asking for this the last time over month. One person even during promotion depending on this service - completely left alone for months.

What does the responsible team (I know its not you) think about other people assessing this? If my boss asks me what FPGAs to buy, I definitely will never recommend a manufacturer that cant even properly run its own software.

Best regards,
Christoph

[AlekhyaV_Intel]

Hi All,

We apologize for the inconvenience caused. Dev Team is looking into it. We will get back to you soon with an update.

Regards,

Alekhya

[AlekhyaV_Intel]

Hi,

The issue is that the incorrect version of Quartus is installed. We have requested that already. Meanwhile, You can work around the issue by adding -DFPGA_DEVICE="Arria10" with the cmake command. Please find the complete command below:

cmake .. -DFPGA_DEVICE="Arria10"

or

cmake .. -DFPGA_DEVICE="Stratix10"

Regards,

Alekhya

[AlekhyaV_Intel]

Hi,

Has the solution provided helped? Could you please give us an update regarding this issue?

Regards

Alekhya

[YuanM]

Thanks, compiling with the Arria or Stratix boards as suggested still leads to a BSP error (on both compile time and run time nodes)

CMake Error at src/CMakeLists.txt:22 (message):
  ERROR: This tutorial requires a BSP that has USM host allocations enabled.

Could this be enabled?

---

@AlekhyaV_Intel wrote:

Hi,

Has the solution provided helped? Could you please give us an update regarding this issue?

Regards

Alekhya

---

[Christoph9]

Hey Alekhya,

do you have information when the new Quartus installation will be installed so we can do Agilex builds? For our paper we wanted to include the newer FPGA generation if possible...

Best regards

[robertszafa]

I am facing similar issues when trying to compile for the Arria 10:

Error (18640): The Quartus Partition Database File '/home/u119070/tmp/histogram_bram_dynamic-470fbd-eb2402/build/dcp.qdb' was generated using version 'Version 19.2.0 Build 57 06/24/2019 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u119070/tmp/histogram_bram_dynamic-470fbd-eb2402/build/dcp.qdb' using the current version of the Quartus Prime Software.
Error (18640): The Quartus Partition Database File '/home/u119070/tmp/histogram_bram_dynamic-470fbd-eb2402/build/green_region.qdb' was generated using version 'Version 19.2.0 Build 57 06/24/2019 SJ Pro Edition', which cannot be read by the current version of the Quartus Prime software. Regenerate '/home/u119070/tmp/histogram_bram_dynamic-470fbd-eb2402/build/green_region.qdb' using the current version of the Quartus Prime Software.
Error: Flow failed: 0x9c0e3c0
Error: Quartus Prime Synthesis was unsuccessful. 3 errors, 233 warnings

[robertszafa]

My issue relating to the incorrect Quartus version can be solved by pointing some environment variables to the correct version (19.2 for Arria 10 FPGAs):

export QUARTUS_ROOTDIR=/glob/development-tools/versions/intelFPGA_pro/19.2/quartus/
export QUARTUS_ROOTDIR_OVERRIDE=/glob/development-tools/versions/intelFPGA_pro/19.2/quartus/
export QSYS_ROOTDIR=/glob/development-tools/versions/intelFPGA_pro/19.2/qsys/bin
export PATH="$QUARTUS_ROOTDIR/bin:$QSYS_ROOTDIR:$PATH"

But the problem described in this thread affecting all Devcloud nodes still persists. I get this error on fpga_runtime and fpga_compile nodes:

"Full compiles to generate hardware for the FPGA are available on supported ..."

Maybe there is a missing Quartus license? The /glob/development-tools/versions/intelFPGA_pro/19.2/init_quartus.sh script sets these environment variables:

export LM_LICENSE_FILE=/usr/local/licenseserver/quartus.lic
export ALTERAD_LICENSE=/usr/local/licenseserver/quartus.lic

 But /usr/local/licenseserver/quartus.lic does not exist. At the moment there are no nodes that can do a hardware compile for the FPGA. @AlekhyaV_Intel your help in fixing this would be greatly appreciated. Hopefully, the above info can help.

[AlekhyaV_Intel]

Hi All,

We apologize for the inconvenience caused. Dev Team is looking into this Quartus issue and we will get back to you soon with an update.

Thanks,

Alekhya

[AlekhyaV_Intel]

Hi,

We appreciate your patience. Regarding the errors on FPGA nodes, we apologize for the inconvenience caused & have forwarded your development experience to our relevant team. As of now, we could provide a possible workaround to compile for emulation (fast compile time, targets emulated FPGA device) using below commands:

qsub -I -l nodes=1:fpga_runtime:ppn=2 -d .

source /opt/intel/oneapi/setvars.sh

cmake ..

make fpga_emu

If this helps in resolving your issue, make sure to accept it as solution. This might help others with similar errors.

Thanks,

Alekhya

[AlekhyaV_Intel]

Hi,

Has the solution provided helped? Can we discontinue monitoring this thread?

Regards,

Alekhya

[ThasneemV_Intel]

Hi,

Since we didn't hear back from you, we assume that your issue is resolved. If you need any additional information, please post a new question as this thread will no longer be monitored by Intel.

Regards,

Thasneem Vazim