Invalid Binary for FPGA Stratix 10 Nodes

[lkljucaric]

I originally posted this question over on the HLS forum; however, I believe this is more DevCloud specific...

I recently built new FPGA images for the DPC++ code I have using the new 2021.3 version of the tools. I had previously built the same source code using the 2021.1 version of the tools and executed the designs on Stratix 10 nodes. I noticed that there are new "fast-math" optimizations for FPGAs with the new version of the tools, so I wanted to investigate the changes.

The compile/synthesis completes successfully, generates all reports, and provides the executable images. When connected to a node with a Stratix 10 device, I run the executable and get the error:

terminate called after throwing an instance of 'cl::sycl::runtime_error'
what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY)
Aborted

Investigating this issue further, I am seeing the same error when trying to execute an example vector add program. Is this something to do with changes to USM/board support package versions?

Command to compile:

dpcpp -I $INTELFPGAOCLSDKROOT/include/ref -qactypes -fintelfpga -Xshardware -Xsboard=intel_s10sx_pac:pac_s10 vecadd.cpp -Xsclock=400MHz -Xsprofile -v -o fpga.hw

Attached is the source code from dpc++FPGA direct programming examples (vecadd.cpp). Compiled on "nodes=1:fpga_compile:ppn=2" node, executed fpga.hw on "nodes=1:stratix10:ppn=2" node. Passes CPU and FPGA emulation.

Full output:

Running on device: pac_s10_usm : Intel PAC Platform (pac_ee00000)
Caught a SYCL host exception:
Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY)
terminate called after throwing an instance of 'cl::sycl::runtime_error'
what(): Native API failed. Native API returns: -42 (CL_INVALID_BINARY) -42 (CL_INVALID_BINARY)
Aborted

[lkljucaric · Accepted solution]

SOLVED:

BSP loaded on device was pac_s10_usm, designs compiled for pac_s10.

To switch BSPs:

aocl initialize acl0 pac_s10_usm or 

aocl initialize acl0 pac_s10

See for further details: https://software.intel.com/content/www/us/en/develop/documentation/oneapi-programming-guide/top/programming-interface/fpga-flow/fpga-bsps-and-boards/fpga-board-initialization.html

[RaeesaM_Intel]

Hi,

Glad to know that your issue is resolved and thank you for sharing the solution.

We are discontinuing monitoring this thread. Please raise a new query incase of further issues.

FPGA Forum link : https://community.intel.com/t5/Intel-High-Level-Design/bd-p/high-level-design

Thanks and Regards,

Raeesa