I spent a week debugging an issue with the FPGA DevCloud resources in this DevCloud forum, receiving feedback from several Intel representatives with no indication that this was the "wrong" forum to diagnose something specific to the FPGA DevCloud nodes. I was confused when my topic was summarily locked without resolution by one of the same support representatives. Now I have to reconstruct that diagnostic information at another forum. If this is indeed not the place to diagnose FPGA DevCloud issues, but only non-FPGA DevCloud issues, that should be stated upfront. (As has been done for Edge, OpenVINO, and Optimized AI Frameworks.)
There remain AOC issues with the arria10 nodes in the default queue, but I am still diagnosing whether they are due to environment configurations I have dragged over from the FPGA queue.
We are extremely sorry for the confusion. We completely understand your concern and will address the feedback provided at the earliest.
Regarding the details already provided in the DevCloud forum thread, kindly give that link as a reference in the new thread in https://forums.intel.com/s/topic/0TO0P0000001AUUWA2/intel-high-level-design?language=en_US, so that you need not iterate the same thing again.