I have Top level-design error on this Verilog code which is for a c-element.
C-element output= OR( AND(A,B), AND(B, output), AND(A, output)). So basically a feedback is used.
Can you please respond to this issue as soon as possible?
This question does not seem to be related to Intel® Edge Software Device Qualification (ESDQ) package. Could you please confirm which Intel product you are using so I can route your question to the correct team?