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AGND and GND connection EN63A0QA

MBaqu
Beginner
1,695 Views

Hello,

 

I would like to know what is the recommandation about the AGND and GND plane connection. Is it recommanded to connect together in a unique point or via multiple vias?

 

Also, is it possible to have the gerber file of the evaluation kit?

 

Thanks

Regards

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1 Solution
SreekumarR_G_Intel
280 Views

You can look at in two perspective

i) Schematic point of view. In Schematic design this two ground (AGND and GND ) must connected together , Internal to the IC I dont think so control circuit is isolated anyways. now you may have question then why two different gnd pin? You can refer the schematic reference from Intel

ii) Lets now take a look in PCB point of view , PCB Designer can split the Gnd plane as form of Island, Example; Single Plane split into two : Power island and Quite island (Less switching current) . The quite island connected to IC AGND and High current Circuitry connected to power Gnd island. This two island must be connected through vias or thin trace to get ground equi-potential. This technique avoids large switching current noise and ground bounce in the control circuitry part of IC.

Here is the link for gerber file link you looking for  

https://buyfpga.intel.com/PartDetail?partId=4430862 

Also go through Design user guide from Intel 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/en63a0qi_evb_user_guide.... 

Thank you 

View solution in original post

2 Replies
SreekumarR_G_Intel
281 Views

You can look at in two perspective

i) Schematic point of view. In Schematic design this two ground (AGND and GND ) must connected together , Internal to the IC I dont think so control circuit is isolated anyways. now you may have question then why two different gnd pin? You can refer the schematic reference from Intel

ii) Lets now take a look in PCB point of view , PCB Designer can split the Gnd plane as form of Island, Example; Single Plane split into two : Power island and Quite island (Less switching current) . The quite island connected to IC AGND and High current Circuitry connected to power Gnd island. This two island must be connected through vias or thin trace to get ground equi-potential. This technique avoids large switching current noise and ground bounce in the control circuitry part of IC.

Here is the link for gerber file link you looking for  

https://buyfpga.intel.com/PartDetail?partId=4430862 

Also go through Design user guide from Intel 

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/en63a0qi_evb_user_guide.... 

Thank you 

SreekumarR_G_Intel
280 Views

Hello there , if you don t have further question on this topic , Can you please close the thread ?

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