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LTosc
Beginner
1,712 Views

ARRIA V GX Hard Power down all Transceivers

I am using ARRIA V GX 5AGXBA1D6F27C6N in my design, which has 9 transceivers. The FPGA is selected for the number of I/Os required. The transceivers are totally unused and need to be hard power down if possible to minimize power consumption.

In AV53003, page 3-18 it is mentioned:

 VCCE_GXBL and VCCL_GXBL must be connected either to the required supply or to GND. The VCCH_GXBL pin must always be powered, but no further information is available. Can I connect to ground all the VCCR_GXBL, VCCT_GXBL, VCCL_GXBL, VCCA_GXBL power pins?

"VCCE_GXBL and VCCL_GXBL must be connected either to the required supply or to GND" it's ok for Cyclone V and not for ARRIA V, isn't it?

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3 Replies
CheePin_C_Intel
Employee
87 Views

Hi,

 

As I understand it, you have some inquiries related to the XCVR power supplies of the AVGX device. For your information, since you are not using any of the XCVR channels, you can connect the VCCR_GXBL, VCCT_GXBL, VCCL_GXBL, VCCA_GXBL power pins to GND.

 

You may refer to the AVGX pin connection guidelines (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/arria-v/pcg-01013.pdf), look for Note 10 of Notes to Arria V GT and GX Pin Connection Guidelines for further details.

 

Please let me know if there is any concern. Thank you.

 

Chee Pin

LTosc
Beginner
87 Views

Hi,

 

many thanks for your answer. Yes, I corfirm it's about XCVR on AVGX. So when all transceiver channels (L,R) are unused, I have the option to connect:

  1. VCCH_GXB[L,R] power pins must always be powered;
  2. VCCR_GXB[L,R], VCCT_GXB[L,R], VCCL_GXB[L,R], VCCA_GXB[L,R] power pins to GND for power saving.

 

Please could you corfim this configuration?

many thanks

Luca

CheePin_C_Intel
Employee
87 Views

Hi, For VCCH_GXB, you can also connect to GND. Best regards, Chee Pin
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