I am designing a cyclone IV device connecting to an ARM processor and DSP. On power up, there is some finite time before the ARM processor would configure the FPGA through passive serial method. The DSP has some signals wired to the FPGA. The DSP may remain in powered down mode until the FPGA is configured. Since the DSP I/O voltages aren't up and because the FPGA I/Os are in weak pull up state prior to configuration, can it damage the DSP pins? Or are weak pull-ups almost synonymous to tristate?
Apologize for delay in response ,
Actually , if you think weakpull might get draw more current than expected , you can change the reset state of IO of FPGA in the quartus prime.
can you please let me know how i can help you out further ?
Thank you ,