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New Contributor I
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EM2120L01QI PMbus pin's capacitance?

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Hi

We are using EM2120L01QI for FPGA core current 0.95V/19.95A. 

1. It is concerned that EM2120's 20A output capability may be to close to max load current 19.95A. Not sure. Our layout is done and PCB is being manufactrued for now. Or could we buy some EM2130 for pin-to-pin backup device?

2. What is the PMbus pin's capacitance?(SCL, SDA, ALERT pins). we need to calculate the Bus capacitanc on PMBUS, but no info on datasheet.

3. It is confusing on page 10 (table 6) and page 32 (table 14), which showed TWO different Max. pmbus clk/data rise time. One is 2ms, another is 300ns. Which one is corret?

4. What is the output current when open-drain SMBUS pins are LOW? that's I(OL). is it 20mA as in page10 table6 ?

5. We use 3 EM2120 for three FPGAs. For each EM2120, they have PVCC(5V), VCC(5V), VDD33(3.3V), is it necessary to connect these conresponding nets fo 3 EM2120 together? or just leave them as independant?

 

Thanks.

 

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Hello Yi Xiao, Please find the answer for your points: 1. Yes, you can replace Em2120L01Qi with EM2130L02QI or EM2140P01QI, where they are all pin to pin compatible. 2. The pins capacitance is less than 5pF 3. Both values are correct and depends on the clock frequency, so the most common frequency is 400kHz and the rising/falling timing around 300ns. 4. The 20mA is the rated pull-up current of the SDA & SALART when the SDA/SALART signal is low which means that the internal FET is on. 5. Please leave each net voltage independent from each other and avoid to connect them together. Regards, Mostafa

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New Contributor I
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1. yes we can use EM2130L02QI for pin-to-pin replacements

5. can be independent. no need to connect them together.

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New Contributor I
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Hello Yi Xiao, Please find the answer for your points: 1. Yes, you can replace Em2120L01Qi with EM2130L02QI or EM2140P01QI, where they are all pin to pin compatible. 2. The pins capacitance is less than 5pF 3. Both values are correct and depends on the clock frequency, so the most common frequency is 400kHz and the rising/falling timing around 300ns. 4. The 20mA is the rated pull-up current of the SDA & SALART when the SDA/SALART signal is low which means that the internal FET is on. 5. Please leave each net voltage independent from each other and avoid to connect them together. Regards, Mostafa

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New Contributor I
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Thanks, Mostafa. All clear.