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EM2280P01Q1 VSEN Pin Connections

rperry
Novice
1,885 Views

Hi Intel,

On the EM2280P01Q1 power module, can the VSEN(P,N) pins be left unconnected/floating in the default configuration mode, or should they be connected?

Regards,

Roger Perry

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1 Solution
Mostafa_Intel_AE
Employee
1,857 Views

Hi Roger Perry,

Attached is the required design files.

Attached also is your schematic after the review.

Your schematic looks ok, but i would suggest to increase the VCC filter cap to 22uF and also enable the remote sensing feature to compensate for the PCB voltage drop at the FPGA terminal.

Please make sure EM2280 PGND is connected to your system GND to avoid any power delivery issues.

Please also get SDA/SCL pints routed to TP incase there is any need for a debug.

 

Thanks,

Mostafa

View solution in original post

17 Replies
Mostafa_Intel_AE
Employee
1,875 Views

Hello Roger Perry,

Unfortunately, VSENP and VSENN can't be left floating where this could damage the module where these two pins related to the feedback loop and making them floating means the regulator will work at the max duty cycle and the output voltage will be close to the input voltage level which will cause a voltage stress over the output caps and the internal controller current sensing circuit resulting damaging all of them.

Thanks,

Mostafa

rperry
Novice
1,867 Views

Hi Mostafa,

Thank you for the feedback.

I have related requests.

1) Can you please review our schematic design for the EM2280P01Q1 module (schematic page attached) and provide feedback?

    Note: Presently estimated max output load is <60A at 0.8V.

2) Can you provide and example PCB layout, possibly from your development board?

Regards,

Roger Perry

Mostafa_Intel_AE
Employee
1,858 Views

Hi Roger Perry,

Attached is the required design files.

Attached also is your schematic after the review.

Your schematic looks ok, but i would suggest to increase the VCC filter cap to 22uF and also enable the remote sensing feature to compensate for the PCB voltage drop at the FPGA terminal.

Please make sure EM2280 PGND is connected to your system GND to avoid any power delivery issues.

Please also get SDA/SCL pints routed to TP incase there is any need for a debug.

 

Thanks,

Mostafa

View solution in original post

Nadine24
Beginner
1,847 Views

Hello Mostafa, 

Thank you for reviewing the schematic and providing your feedback. I am working with Roger Perry on the board design and would have a follow up question in regards to your feedback. 

You mentioned that the VSENS lines should be connected to the FPGA Vsens pins. Our FPGA in the system doesn't support remote sense pins so any voltage adjustment couldn't be performed. 

Is it sufficient to connect the VSENP via a 0 Ohm resistor close the FPGA pins the Intel regulator is providing Vout for ?

Thanks,

Nadine 

Mostafa_Intel_AE
Employee
1,839 Views

Hello Nadine,

You are welcome.

Since i don't know how far is the FPGA will be from the regulator and also i don't know if there is any other decoupling caps (which i expect there will be at lease 1mF decoupling other than the local output capacitance required by the regulator), so i would suggest that you keep the local sensing (which will located right after the local output caps of the regulator) through 100R beside connecting the remote sensing through 0R to the closest point to the FPGA VCC pins which will help to compensate for the voltage drop across the PCB.

Also since your FPGA doesn't have internal sense points then you can use only the remote sensing if the distance between the sense points and the regulator less than 2inchs (or the trace inductance<10nH)

 

Thanks,

Mostafa

 

Nadine24
Beginner
1,836 Views

Hello Mostafa, 

Thank you for your quick reply. 

Yes the FPGA as over 5mF of decoupling caps on this supply. 

The regulator right now is approx. 8 inches away from the FPGA but I can move it closer to the FPGA. 

I just would like to confirm that I understood your VSENP/VSENn connection correctly. 

Below quick drawing is showing my understanding now:

Nadine24_0-1607977664213.png

Is that accurate ?

Thanks,

Nadine 

Mostafa_Intel_AE
Employee
1,834 Views

Hello Nadine,

Yes, your drawing is correct and that local sensing should be right after the local output caps.

I recommend that connection since the FPGA will be far from the regulator and the 0.85V trace will have high inductance that will effect the control loop.

If you can reduce the distance between the regulator and the FPGA that will help to improve the system performance.

Thanks,

Mostafa

Nadine24
Beginner
1,811 Views

Hello Mostafa, 

Thank you. Why is the local sense resistor of 100 Ohm needed when using the remote sensing close to the FPGA ? 

Are they not interfering with each other than ?

Thanks,

Nadine 

Mostafa_Intel_AE
Employee
1,801 Views

Hello Nadine,

The 100R resistor need for local sensing to make sure that there is some impedance difference between the local and the remote sensing to allow the remote sensing to compensate for the voltage drop, but the local sensing will help to maintain the system stable.

Thanks,

Mostafa

Nadine24
Beginner
1,796 Views

Mostafa,

Okay thank you for all your help.

Best regards,

Nadine 

Nadine24
Beginner
1,656 Views

Hello Mostafa, 

I hope you are doing well. I am looking at the reference design and the datasheet of the EM2280P01Q1 again and have a question in regards to the AGND connection. 

It looks like only the square in the middle of the regulator is considered as AGND but is connected via via's to the PGND layers.  On the reference layout the RVSET and RTUNE resistor are just connected to the PGND layers and not directly connected to AGND flood underneath the part. 

So AGND is only not connected to PGND on the top layer but connected to all inner PGND layers is my understanding correct ? Therefore RVSET and RTUNE can be connected just to PGND. 

 

Thanks,

Nadine 

 

Mostafa_Intel_AE
Employee
1,650 Views

Hello Nadine,

Thanks a lot, I am doing well, and i hope you are doing well too!

Regarding AGND connection, it is as you descried connected to PGND through a single via or through 0R to improve the noise rejection and avoid the noise coupling between AGND and PGND.

So regarding RVSET and Rtune GND's connection, it is better to connect them to AGND, but connecting them to PGND will not effect the controller noise rejection where RVSET and Rtune pins are high impedance pins and only used during the boot up to determine the Vout and compensator multiplier.

 

Thanks,

Mostafa

Nadine24
Beginner
1,640 Views

Hello Mostafa, 

Thank you for your quick reply. I am doing well too. 

Just to clarify it looks like that the AGND connection is being done via multiple top to bottom via's connecting to each GND layer. 

Besides the Top layer I don't see any separation of AGND to PGND. 

Ba

Thanks,

Nadine 

 

Nadine24_0-1612876455395.png

 

Mostafa_Intel_AE
Employee
1,632 Views

Hello @Nadine24 ,

 

I am sorry if i confused you by my pervious answer which consider a general design rule.

But for EM2280, The little square underneath the package actually is PGND not AGND, this why it is fully connected to PGND.

Regarding AGND, it  is connected to PGND on substrate level and it is not routed externally.

Please let me know which of our documents mention that small square pad is AGND, so we can update that document.

 

Thanks,

Mostafa

Nadine24
Beginner
1,628 Views

Hello Mostafa, 

Okay thank you that makes more sense.

I have attached datasheet. Figure 7 shows AGND and also the layout guidelines are referring to AGND in some sections. 

Thank you again for your quick help. 

Best regards,

 

Nadine 

Nadine24
Beginner
1,098 Views

Hello Mostafa, 

I wanted to reach out to your again to see if you have any idea what could be the reason for the strange behavior we saw but currently can not reproduce on our board anymore. 

We implemented the EM2280 on our board design based on the schematic you have reviewed in the past. The part works great and supplies the core voltage to the FPGA. 

I did have 1x board were the EM2280 didn't even try to bring up the output voltage and I am wondering now if any of the unused pins in the design could cause the EM2280 to not boot-up. 

The control pin was high and the regulator was enabled but I was not able to measure any PWM output or Vout. The issue disappeared now and I can not reproduce it anymore.  The schematic can still be seen in the above communication. 

 

Thanks,

 

Nadine 

 

 

Mostafa_Intel_AE
Employee
1,091 Views

Hello Nadine ,

 

Probably there was a temporary short circuit on the board and once that short go away the part able to startup.

 

There are three reasons that could make the part can't startup:

  1. VCC voltage <4.5V
  2. CTRL is low
  3. OCP triggered (short circuit)

So if you are sure that the VCC and CTRL signals are high, then it will be a short circuit issue.

 

Thanks,

Mostafa

 

 

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