EV1340QI Hiccup mode

[ravi1]

Hi,

We are using EV1340QI for providing regulated power supply to QDR (CY7C1514KV18-333BZI). This was working and not a new design. Recently we have purchased 12 digital boards and found that the output of EV1340QI is in hiccup mode(output is pulsing @ 20mS rate, 0.9Vp-p), and the defect is same in all digital boards. we also verified the short circuit condition and over load condition and found to be fine.  Request to suggest way ahead.

Thanks in advance

[Mostafa_Intel_AE]

Hello Ravi,

probably that issue related to inrush current due to higher output capacitance.

To control the inrush current, you will need to slow down the VDDQ ramping up during the startup or reducing the output loading capacitance.

Also please increase the Css which will give some delay for the VTT ramping too.

So if it possible to share a waveform for the startup and probe the VDDQ , VTT and Css

Could you please help to share EV1340 schematic and what is the total output capacitance attached till the DDR?

Thanks,

Mostafa

[ravi1]

Hi mostafa,

As requested schematic and pulsing waveform attached for reference. kindly suggest way ahead. Important observation is that its not a new  design.

Thanks in advance

[Mostafa_Intel_AE]

Hi ravi,

Thanks a lot for sharing the hiccup measurement and EV1340 schematic.

It looks the issue related to the soft start, please help to probe 3V3, 1V8, VTT_EN and VREF signals during the startup for review.

Please Use the VTT_EN for scope trigger channel.

Thanks,

Mostafa

[ravi1]

Hi Mostafa,

3V3: stable DC state

1V8: stable DC state

VTT_EN: stable pull up DC state

VREF: Pulsing @20mS, 0.6Vpp, waveform same as VTT (already shared)

Imp observation:

1) EV1340QI -- (Date/batch code: E01CR found to be non-working, Year of issue: 2019)

2) EV1340QI -- (Date/batch code: E01QH found to be working (old spare IC available with us), Year of issue: 2011-13 appx) 

Please help to resolve the issue.

Thanks in advance

Regards,

Ravi

[Mostafa_Intel_AE]

Hi Ravi,

Thanks for your feedback.

I understand that you saw that issue with the latest data code but it doesn't matter where the OCP level has some variation from one device to another.

I need the requested measurement to confirm the starting up timing based on the VREF ramping timing.

I understand the VTT will track the VREF signal and also in same time it will track the VDDQ signal which is controlling the startup timing.

Based on schematic there is a power on sequencing issue which will generate a high inrush current that will trigger the OCP.

So please help to probe 3V3, 1V8, VTT_EN and VREF signals during the startup and please zoom out so i can be able to check the starting timing.

Please use VTT_EN to trigger your scope for the first power on cycle which i need to do analysis for it.

Thanks,

Mostafa

[Mostafa_Intel_AE]

Hi Ravi,

Do you have any update?

Thanks,

Mostafa