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Hi ,
I recommend you to refer the power down and power up sequence in Arria 10 . And design the board with the recommendation given below in the document.
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf
Regards,
RS
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Hi,
Thank you for your answer.
What I'm trying to find out is: what happens with the FPGA if I lose the power supply of VCCERAM during the use of the FPGA, for example !?
Regards,
Amaury
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Hi ,
Please check the page no 325 of the below document , in that VCCERAM is monitored by POR so the power cannot be taken out
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_handbook.pdf
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