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Help in translating lines of code verilog to vhdl

CHerb4
Beginner
916 Views

Greetings, first to say that I am new to the forum and I really do not know if this is the correct section for this type of questions.

I have limited knowledge in vhdl but I am totally new in verilog. A couple of days ago I try to translate a project from verilog to vhdl, for this I am using a translator, but even so I am finding the following lines that I can not translate to vhdl.

 

`define SBUSRANGE 32*idx+31:32*idx // Incrementing indexes within generate below   wire [31:0] sdma_dq = i_sdma_dq[`SBUSRANGE];

Any help is very welcome, thanks in advance.

 

 

 

 

 

 

 

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1 Reply
GuaBin_N_Intel
Employee
193 Views

Maybe you can try out line below:

 

=> signal [31:0] sdma_dq : std_logic_vector ((32*idx + 31) downto (32*idx));

 

 

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