Greetings, first to say that I am new to the forum and I really do not know if this is the correct section for this type of questions.
I have limited knowledge in vhdl but I am totally new in verilog. A couple of days ago I try to translate a project from verilog to vhdl, for this I am using a translator, but even so I am finding the following lines that I can not translate to vhdl.
`define SBUSRANGE 32*idx+31:32*idx // Incrementing indexes within generate below wire [31:0] sdma_dq = i_sdma_dq[`SBUSRANGE];
Any help is very welcome, thanks in advance.