We have been running prototype HW for many months. After cycling power, our PWB no longer functions properly. The problem has been isolated to the FPGA which can no longer be accessed via JTAG.
We need to understand more about your Failed Max 10 device before you can send for diagnostic testing and failure analysis.
Did you have any failure symptoms? (get any error or warning in Quartus)
Did you checked the power for JTAG pin? (TCK, TMS, TDO, TDI n etc2) Any strange behavior?