I have different power domains in my board..My FPGA is not the earliest chip to power up. So there would be a bunch of signals going to my GPIO of the FPGA that is in power off mode(no power to FPGA at all). In long term run, would this damage my FPGA or not. I checked the IO structure on page 12 of this doc Intel® MAX® 10 General Purpose I/O User Guide. But I am still not very sure if this will cause any problem or not. Please help!
