I have a hardware design that uses 10AS057 FPGA with heatsink (with still air).
On my Early power estimator (EPE), the RRU- FPGA estimated total power 9W. I've run the RRU unit in room temperature and the FPGA power consumption at 0.95V rails is 7.54W which is good.
However, I've placed the RRU unit in temperature chamber and run at 40degC the FPGA power consumption at 0.95V rails increases to 14.5W and continuously increasing (PSU current limit is 20A). I measured the Tcase of the FPGA at 40degC ambient and the Tcase is 89.3degC.
The FPGA power consumption at 0.95V from 7.54W to 14.5W is a big jump in temperature- given that we have current limit on the PSU of 20A in which EPE shows only 9W of total power cosumption.
I would like to know what is causing this jump in power consumption (7.54W to 14.5W) at temperature at the FPGA side -specifically at 0.95V rail.
I would like to know the solution for the issue stated above -either PSU solution, thermal solution, HW or SW solution to stabilize the power consumption (in temperature) of the FPGA.
Intel Support reply:
OK thanks. The single wire test results will be very helpful, to see how they correlate with our Pstatic only estimates.
Can you share your board schematics in the meantime, for a cursory review?
At room temp, EPE = 9W, actual = 7.54W
At 40C, EPE = ??, actual = 14.5W
May I know what is the EPE reading at 40C, I would expect it would increase as well.
Reason: Pstatic commensurate with temperature.
Suggestion: In your EPE, for "power charateristics", please select "Maximum". Make sure for your dynamic loading, you didnt change anything.
Sorry for the delayed response.
As I didnt received your EPE file, i had created one on my own and try to mimic as much as i can from your screenshot.
With the parameters you have given, I have tried changing from Ta 25C to 40C, and i dont see the drastic change as you mentioned.
The only way i can get the EPE to jump is when I change the Theta-ja and Theta-jb to be higher (worse thermal conduction).
Im inclined to think that the EPE parameters you entered may not be the actual board parameters, thus you cant get a correlation.
My guess is that your heat dissipation either by heatsink/airflow or board, may not be as you entered in the EPE.
It makes sense if the heat is not dissipating well, the FPGA Tj increase, leads to higher Pstatic, and higher Pstatic leads to higher Tj, so on and on until it hits a saturation/equilibrium.
You can test my analysis by making the heat dissipation worse, and power dissipation jump even higher. Or you make it better, and you can see the power consumption drops.
I hope this helps.
Hi @CRubi ,
As previously hypothesized, the main reason for your EPE not matching to your actual is that actual may not be dissipating heat as well as what you entered in the EPE. I assumed your dynamic power numbers are correct.
When I tweak your ThetaJB assuming your board cannot dissipate very well, changing both the Ta and Tb from 25C to 40C...that kinda match with your actual results. You may double check with your thermal analysis what is your board thermal dissipation coefficient.
At 25C, 10.8W
At 40C, 14.2W