Why is our MAX10 FPGA responding to wrong JTAG TCK edge here?

[MSchu50]

I am not sure which is the right category for this question, i am sorry.

We are InCircuitProgramming two MAX10 devices in a chain on an embedded board via JTAG. That works in general, but sometimes we are experiencing problems.

Our problems can be explained by a misbehaviour of one of the Intel FPGAs. As you can see on the logic analyzer screenshot at 4.374 ms, the FPGA responds to a rising TCK edge as if it was (also) a falling one.

Is this a known behaviour? What are possible reasons for that? What can we do against it?

[ShafiqY_Intel]

Hi MSchu50,

Have you pull-down TCK pin to 1kOhm?

Thanks

[MSchu50]

Hi WolfGang,

thanks for your reply,

we have tried with and without 1K PullDown on TCK (and 1K PullUp on TMS).

Unfortunately it didn't solve the problem.

[ShafiqY_Intel]

How much the TCK Frequency you are using?

My recommendation, use 6MHz (default value) for TCK Frequency.

And check this pins:

• TDI & TMS = pull-up (10K Ohm)
• TCK = Pull-down (10K Ohm)
• TDO = leave unconnected or pull-up

Cheers

[MSchu50]

Thank you for the suggestions!

Our TCK Frequency is quite slow, around 2 MHz. Maybe this is why we treated it as a "slow" signal and didn't care about enough.

In the meantime our hardware engineeres had a closer look on the (analog side of the) problem and found "something". We are not sure yet but i seems our layout is "too bad" and we ignored termination issues.

[ShafiqY_Intel]

Hi MSchu50,

I hope my previous responses have been sufficient. Thus, I request to close this forum at this time.

Thanks.

[MSchu50]

Hi WolfGang,

yes, thanks, please close. Or can I do anything to close it?