I am not sure which is the right category for this question, i am sorry.
We are InCircuitProgramming two MAX10 devices in a chain on an embedded board via JTAG. That works in general, but sometimes we are experiencing problems.
Our problems can be explained by a misbehaviour of one of the Intel FPGAs. As you can see on the logic analyzer screenshot at 4.374 ms, the FPGA responds to a rising TCK edge as if it was (also) a falling one.
Is this a known behaviour? What are possible reasons for that? What can we do against it?
Thank you for the suggestions!
Our TCK Frequency is quite slow, around 2 MHz. Maybe this is why we treated it as a "slow" signal and didn't care about enough.
In the meantime our hardware engineeres had a closer look on the (analog side of the) problem and found "something". We are not sure yet but i seems our layout is "too bad" and we ignored termination issues.