This is seen on Windows Quartus prime pro version 17.1 programmer via USB Blaster II cable. I am trying to program FPGA on stratix 10 GX development board.
I suspect your TCK frequency might be the root cause here.
Can you kindly try to reduce your TCK frequency to 6 MHz (default value)?
Below link is the command to change TCK frequency (on page 14= "2.8. Changing the TCK Frequency")
Kindly try it out with your design and let me know the result.
Hi, I have the same problem when i try to program a max10 fpga in a new board developed by the hardware team. I don't how can I change the tck frequency because I am new about tcl scripting. Could you help me to set the right clock using tcl scripting? I have 17.0.0 Build 595 04/25/2017 SJ Lite Edition installed.
I tried setting the download cable frequency to 6Mz
PS C:\intelFPGA_pro\17.1\qprogrammer\bin64> .\jtagconfig.exe --setparam 1 JtagClock 6M
PS C:\intelFPGA_pro\17.1\qprogrammer\bin64> .\jtagconfig.exe
1) USB-BlasterII [USB-1]
Captured DR after reset = (0041481BBC32150DD) 
Captured IR after reset = (0AAC01) 
Captured Bypass after reset = (2) 
Captured Bypass chain = (2) 
JTAG clock speed 6 MHz
However I still get the code 35 error:
I'm apologize for late reply.
Here's the comment from my colleague:
" I found that this "error code 35" was caused to due to a network issue at the customer's end. Turning off the network switch helped to program the board successfully."
I hope this will help you to move forward.
Thank you for the follow up. We have tried turning off the network connection but the problem persists. However, we found out that the FPGA chip we have on board is different from our counterpart who generates the FPGA image. They seems to have the Engineering release version while we have the released version.
FPGA team facing issue regenerating IP FPGA image on this specific FPGA chip. We are aligning the FPGA HW version with FPGA team so that we won't hit this issue again.