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I wonder that do ı have to change the referance clock (for cpld) from sinuse to PWM ?



According to spı protocol, ı need 100 Mhz SCKI clock frequency. However when the code is runned, PWM signal has an oscillation. (also occured at 25MHz, 50Mhz). The input clock frequency is 100MHz generated by active sinuse osilator.

USED Programable device is EPM570T100C5 

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