Intel® FPGA Software Installation & Licensing
Installation and Licensing that’s includes Intel Quartus® Prime software, ModelSim* - Intel FPGA Edition software, Nios® II Embedded Design Suite on Windows or Linux operating systems.
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New Project: ElectricPiano_00_00, Request a review of what's wrong.

OJin0
Beginner
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This is a new project to identify problems.

(New project: ElectricPiano_00_00)

 

Hello, Quarters Prime 19.1 behavior is strange.

Attach the project folder.

Request a review of what's wrong.

 

content of project;

It is a frequency divider for the scale of an electronic piano, and the frequency of each output is completely different from the design intention.

 

 

Best regards,

Oksang

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OJin0
Beginner
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Hello, even when one channel (4C_261) is replaced with a 74160 symbol, the normal frequency (261 Hz) is not output.

Where are there any problems? (Design? Or symbol? Or compile? Or assemble?)

 

I have attached the project folder.

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OJin0
Beginner
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Hello,

Attach the message log file of the new project ElectricPiano_00_00.

 

Thank you.

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OJin0
Beginner
820 Views

This is a simulation wave illustration of New Project ElectricPiano_00_00.

 

Thank you.

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SyafieqS
Moderator
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Hi Oksan,

 

What do you mean the Quartus behavior is strange? Can you elaborate it? Is it only for 19.1 or other version behave the same? Have you tried on other version?

 

Thanks,

Regards

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OJin0
Beginner
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Hello,

Right now, I'm using version 19.1 only.

 

We found clues that differed between the function of the schematic and the simulation result.

As below.

 

Like Schematic, inst7 (DFF) is normal when triggered on X3 output.

However, in the currently simulated wave picture, inst7 (DFF) was triggered on X2.

In the PIN_F12 terminal of the board, 261Hz is output if it is normal as in the schematic, but the current 522Hz signal is actually doubled.

Why are they different from the schematic and simulation results?

 

I have attached the current project folder.

 

Thank you.

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OJin0
Beginner
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Hello, In ElectricPiano_00_00, LPM_COUNTER has no problem at all. 50MHz input, 1/50 divided, 1MHz accurate output. OK. However, there is a problem with the array of four synchronous counters (74160). The output of the 4th counter does not output at the designed frequency. There is an error in the simulation result, and there is also an error in the actual board output. Below is my post on the forum. - Below - " Right now I'm using version 19.1 only. We found clues that differed between the function of the schematic and the simulation result. As below. Like Schematic, inst7 (TFF) should be triggered on X3 output to be normal. However, in the currently simulated wave picture, inst7 (DFF) was triggered on X2. In the PIN_F12 terminal of the board, 261Hz is output if it is normal as in the schematic, but the current 522Hz signal is actually doubled. Why are they different from the schematic and simulation results? I have attached the current project folder. " Thank you.
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OJin0
Beginner
820 Views

Project folder

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OJin0
Beginner
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In the schematic, 12 output signals of each scale divider are designed to be shaped by 50% duty waveform by TFF.

However, it was not shaped for 50% duty on the simulation wave.

That is, the function of TFF did not work.

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