Questa Licence Mapping ISSUEfor Starter Edition from Quartus FPGA Software

[BansariK]

Hello there,

I am having an issue were I am using Questa version 24.2 to simulate for Quartus version 24.2. I am getting the issue where it says,

after setting all ENV VAriables in Licence file .

Please help on same. 

[AR_A_Intel]

Hello

Welcome to INTEL forum. Could you upgrade both license vendor daemon software to the newer version and try it.

https://www.intel.com/content/www/us/en/software-kit/709649/license-daemon.html       

Please stop and restart the after upgrade. Shutdown/kill all the license service and restart back from ground zero.

[BansariK]

Hi, 

I am using Intel Quartus FPGA pro 24.2. and provided licence files to in both for quartus and Questa FPGA Edition. 

In the NiosV-shell command using the "vsim" i couldnt open the Questa FPGA edition.

we are not using any SIEMEN Questa licence file in this tool time of setting ENV Variable for Quartus and Questa Starter FPGA Edition. 

as you said i have to go through this link  but  there was  siemen Questa relevant i think so. I don't know i have to use as you suggested or that don't required in my case. 

please elaborate how i can map the licence ?

Thanks,

Bansari

[AR_A_Intel]

Hi

You may refer to KDB here : https://www.intel.com/content/www/us/en/support/programmable/articles/000099465.html

[BansariK]

Hi Everyone,

as i can tell you first that questa was opening up and i can compile the design code and stimulate with waveform. 

but, this case i was addding up UVM testbench files . so compile was coming clean but in time of simulation. i was facing issue 

# Loading C:/intelFPGA_lite/23.1std/questa_fse/uvm-1.1d\win64\uvm_dpi.dll
# ** Error: Failure to checkout svverification license feature.
Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup).
#    Time: 0 ps  Iteration: 0  Instance: /tb_top File: C:/../BKansagara/../Work Data Slot/Questa_PROJECT_ALU/testsv/tb_top.sv

I had done like : 
1) i had installed software and I only got the license.dat file to activate Quartus Prime and Questa,

2) I set an environment variable pointing to that file.

3) i can do compile clean for design and top testbench module of uvm.

4) simulation with this Error (waiting here to come in conclusion)

as, I had searched in internet, so I got result for this issue on  : 

Error: Failure to checkout svverification license feature.
Fatal: (vsim-7099) Unable to check out a verification license for the randomize() feature.

Comment on this error (internet): As far as I was able to understand, that's one of the limitations of Starter Edition. is it so?

I am sharing the screenshot as well. can anyone please help me on the same?

Thanks,

Bansari

[AR_A_Intel]

Hi

Yes, it appears that both Questa*-Intel® FPGA Edition and Questa Starter Edition does not support advanced verification features.

https://www.intel.com/content/www/us/en/docs/programmable/730191/24-1/comparing-simulator-versions.html

Customer may need Siemens EDA Questa Prime to perform advanced verification and could be purchase at Questa/Siemens and their partners.

[AR_A_Intel]

As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/s/?language=en_US , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.