2 to 1 Multiplexer Codes

[Altera_Forum]

I am going to post my VHDL codes for a 2 to 1 Multiplexer,im not sure if im heading the right way or not but i would like to get some feedback on what im doing. 

 As you can see. SW(8) is my s input and SW0-SW3 is my x input and SW4-SW7 is my y input.Im using a DE1 board.   library ieee; use ieee.std_logic_1164.all;  entity chiong1 is PORT( SW :IN STD_LOGIC_VECTOR (9 DOWNTO 0);  LEDR :OUT STD_LOGIC_VECTOR (9 DOWNTO 0);  LEDG :OUT STD_LOGIC_VECTOR (3 DOWNTO 0)); end chiong1;  architecture Behavior of chiong1 is SIGNAl M : STD_LOGIC_VECTOR (3 DOWNTO 0); begin   M(3) <= (NOT (SW(8)) AND SW(3)) OR (SW(8) AND SW(7));  M(2) <= (NOT (SW(8)) AND SW(2)) OR (SW(8) AND SW(6));  M(1) <= (NOT (SW(8)) AND SW(1)) OR (SW(8) AND SW(5));  M(0) <= (NOT (SW(8)) AND SW(0)) OR (SW(8) AND SW(4));   LEDG(0) <= M(0);  LEDG(1) <= M(1);  LEDG(2) <= M(2);  LEDG(3) <= M(3);    LEDR(0) <= SW(0);  LEDR(1) <= SW(1);  LEDR(2) <= SW(2);  LEDR(3) <= SW(3);  LEDR(4) <= SW(4);  LEDR(5) <= SW(5);  LEDR(6) <= SW(6);  LEDR(7) <= SW(7);  LEDR(8) <= SW(8);  LEDR(9) <= SW(9);   end Behavior;

[Altera_Forum]

What you are doing makes your code hard to read and difficult to understand. Theres also a very useful VHDL construct for muxes 

 why not separate it out so it reads alot easier:  port ( s : in std_logic; x : in std_logic_vector(3 downto 0); y : in std_logic_vector(3 downto 0);  op : out std_logic_vector(3 downto 0); );   architecture.... begin  op <= x when s = '0' else y; end.

[Altera_Forum]

thanks for the feedback tricky 

 i was wondering whether do i add   LEDR into my ENTITY,so that when i switched on s,x and y,the red lights will be switched on as well,so that it would be clear to the observers that the switch is turned on? or is there any simpler ways to do that?  entity..... LEDR:out std_logic_vector(9 downto 0);  architecture .....  LEDR<= s,x,y;

[Altera_Forum]

--- Quote Start ---    LEDR<= s,x,y;  --- Quote End ---     LEDR <= s & x & y;