3 to 1 Multiplexer Codes

[Altera_Forum]

Here is my 3 to 1 Multiplexer Codes,from the instructions it was said that it must be built through a 2 to 1 Multiplexer and an extra input 

 SW(8) and SW(9) are my inputs SW0-SW1 are my U,SW2-SW3 are my V and SW4-SW5 are my W  Tell me what do you think?   library ieee; use ieee.std_logic_1164.all;  entity chiong2 is PORT( SW :IN STD_LOGIC_VECTOR (9 DOWNTO 0);  LEDR :OUT STD_LOGIC_VECTOR (9 DOWNTO 0);  LEDG :OUT STD_LOGIC_VECTOR (1 DOWNTO 0));   end chiong2;  architecture Behavior of chiong2 is  SIGNAL FLOP :STD_LOGIC_VECTOR(1 DOWNTO 0);  SIGNAL TURN :STD_LOGIC_VECTOR(1 DOWNTO 0);    begin       FLOP(1) <= (NOT (SW(8)) AND SW(1)) OR (SW(8) AND SW(3));  FLOP(0) <= (NOT (SW(8)) AND SW(0)) OR (SW(8) AND SW(2));      TURN(1) <= ((NOT (SW(9)) AND FLOP(1)) OR SW(5)) OR (SW(8) AND SW(5));  TURN(0) <= ((NOT (SW(9)) AND FLOP(0)) OR SW(4)) OR (SW(8) AND SW(4));    LEDG(0) <= TURN(0);  LEDG(1) <= TURN(1);   LEDR(0) <= SW(0);  LEDR(1) <= SW(1);  LEDR(2) <= SW(2);  LEDR(3) <= SW(3);  LEDR(4) <= SW(4);  LEDR(5) <= SW(5);  LEDR(6) <= SW(6);  LEDR(7) <= SW(7);  LEDR(8) <= SW(8);  LEDR(9) <= SW(9);    end Behavior;

[Altera_Forum]

since I've learnt some simplified ways,am i going the right way with this? 

does it represent 3 to 1 mux?  library ieee; use ieee.std_logic_1164.all;   entity chiong2_1 is port (s : in std_logic_vector(1 downto 0);  u : in std_logic_vector(1 downto 0);  v : in std_logic_vector(1 downto 0);  w : in std_logic_vector(1 downto 0);  red:out std_logic_vector(7 downto 0);  op : out std_logic_vector(1 downto 0));  end chiong2_1;   architecture behavior of chiong2_1 is begin  red<= s & u & v & w;  op<= u when (s(0) ='0' and s(1) ='0') else   v when (s(0) ='1' and s(1)='0') else  w when (s(0) ='0' and s(1) ='1') else  w;   end behavior;