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Write a VHDL code to design a universal binary counter
Assign the I/O ports to the boards I/O pins as follows: Design I/O port Board I/O pin
Clock (clk)
CLK_50M
Enable (en)
V_SW(0)
Count up (up)
V_SW(1)
Clear (syn_clr)
V_BT(0)
load
V_BT(1)
Output (q)
G_LED (3 downto 0)
Input (d)
V_SW(5 downto 2)
Synthesize the circuit and upload it to the FPGA prototyping board.
Verify the operation of counter.
Hint: you will need to slow down the main clock frequency (50MHZ) to see the LEDs blinking pattern. Use cycle counter to control the counter operations.
Max Count = Max Frequency/Desired Frequency
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Hi Qais Jamal
Thanks for your sharing. Let us know if anything we could help you.
Thanks.
Eng Wei
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I want a VHDL code to design a universal binary counter and apply it on FPGA at LabsLand
if you can help me
Thank you.
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I want a VHDL code to design a universal binary counter and apply it on FPGA at LabsLand
if you can help me
Thank you.
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Hi Qais
There are few links from Intel providing design example for counter as below:
https://fpgacloud.intel.com/devstore/platform/
Else, you can also search for 3rd party design and modify per your usage.
Thanks.
Eng Wei
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Hi Qais
We do not receive any response from you to the previous answer that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei

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