Could we consult with you about HW strapping of this pin (ADC_VREF_D3) of 10M04SAU169C8G
Actually, we didn’t use this pin in our current design, so left it to ground as snapshot at that moment and unfortunately, PCB had been T.O.
(In general, we know that if this pin is not being used for ext. reference, let it to NC), but some gaps during BRD development, so
Could you please advise any potential risk depending on the connection of ADC_VREF_D3 to GND due to we worried that and not sure what kinds of the impact would be occurring to FPGA activity once connect this pin to GND, even we can control this pin by coding.
First of all the ADC_VREF pin is an dedicated pin (reference page no:13 ) and is used a s Analog to digital voltage reference input.
If is is connected to GND, I do not have any characterization data for the impact. . Definitely it will effect the ADC (if using) .
With respect to reliability, there is not data point I have