I have a design for a simple NIOS II processor on the DE1-SoC board that assigns the value on the switches to the LEDs (standard hello world) but this design integrates the SDRAM on the board into it as per this tutorial using the sdram on altera’sde1 board with verilog designs.
I have ensured that the reset and exception vectors and interconnects are as per the tutorial, however when I attempt to load the current configuration and start the debug session i get the following error:
Using cable "DE-SoC ", device 1, instance 0x00 Resetting and pausing target processor: FAILED Leaving target processor pausedI guess the SDRAM is causing some problem when the processor tries to come out of reset, but I can't work out how... Does anyone have any suggestions?
I've seen that message when I had a bad configuration file, or when I forgot to load the FPGA configuration before starting the monitoring program. You can narrow it down by seeing if the board works with a known good configuration file.
I have tried restarting the Altera Monitor Program, and ensuring I use the quartus programmer to flash the device before I start the monitor program, this still gives the same problem. If I don't use the SDRAM controller in the qsys design and instead use on-board RAM or ROM for the reset and exception vectors then the system works. Which makes me suspicious of the SDRAM components. However if I use some test code that uses an SDRAM controller and periphery (but with no NIOS) then that program works ... so i suspect the SDRAM isn't broken...# ######EDIT####### I have also revisited all of the settings for the SDRAM controller to make sure they match those in the tutorial and even tried both the NIOS II Classic and the NIOS II 2nd Gen cores however I still get the same error. Incidentally I'm not actually looking at using the SDRAM with a NIOS II controller, instead I would like to be able to have an interface where I can just write a value to a location in the SDRAM and then have a VGA controller reading the contents of the SDRAM and displaying on a screen, so if anyone has any more specific tutorials/information/reference designs for this then that would be most useful!
Hi, I assume that the SDRAM will act somewhat like a frame buffer, and the RTL will just continuously read from there and output it (something like RAW2RGB ). If this is the case, take a look at Terasic's example for D5M:http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&categoryno=68&no=281&partno=3 Perhaps you can modify the code from thence.