Altera UP Flash Memory IP Core, Standalone Interface - any experience?

[Altera_Forum]

Hi all, 

 I am trying to access the flash memory in Altera/Terasic DE2 dev board with the standalone interface flash memory IP Core (that doesnt use Nios/avalon) ftp://ftp.altera.com/up/pub/altera_material/9.1/university_program_ip_cores/memory/flash_memory_ip_core.pdf). I could not find the IP core code at Altera’s site but it was available on the internet on other locations.   My initial test is just to read from the first memory address. I hold the reset signal low (active low) for approx 0.25s to secure a reset and then I read from the address after pushing a push button on the board. Very basic and simple. Please see attached vhdl files (sound.vhd is the top level).   My key issues: 1) When I check for the flash memory DONE signal to be high (line 200, 202) I never get through – the signal appears to be always low.  2) When I comment out the DONE signal check and simply send a READ signal I get all kinds of random address content returned.   Can anybody easily spot if I have made beginners mistake in interfacing with the IP Core. I have not found any application examples that use your IP Core so I am at lost at the moment.   Best Regards /mattias

[Altera_Forum]

Please - everyone, don't spend energy on this one. I implemented my own memory controller instead (with the inspiration from another thread).

[Altera_Forum]

I am so interested on a memory controller, could you post the code that you implemented? It would be so helpful, thank you in advance.

[Altera_Forum]

--- Quote Start ---  Please - everyone, don't spend energy on this one. I implemented my own memory controller instead (with the inspiration from another thread).  --- Quote End ---    Hey, Can u please post the link of the thread where you got your inspiration from!  Thank you