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Honored Contributor I
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Altera_UP_Flash_Memory_UP_Core_Standalone

Hello,  

on a DE1 board, I am trying to write some data into the flash memory and then read them in "hardware" ( don't want to use a processor for this task).  

I know that write operations to flash require a complex procedure, so i searched for a controller and I found the memory controller by altera.  

I got few questions, since I didn't read all the sources in the file: 

1) is enough to porovide write address, data and then set "write" pin high to write a byte into a flash address, using this controller? 

2) I suppose this should not behave like a dual port ram. I mean, i can separately read OR write.  

3) is it necessary to erase stored data before writing new data? 

 

Lou. 

 

EDIT: 

I wrote a simple "interface" for tring to test flash memory.  

 

--- Quote Start ---  

 

module interface_to_flash(  

iCLK, 

iRST, 

iStart, 

iValid, 

iDone, 

oCounter, 

oEnable, 

oData 

); 

// Host Side 

input iCLK; 

input iRST; 

input iStart; 

input iDone; 

input iValid; 

// FLASH Side 

output reg oEnable; 

output reg [20:0]oCounter; 

output reg[7:0]oData; 

//paramteters 

parameter ADDRESS = 21'H1ffff0; 

// Internal Registers/Wires 

reg [1:0] fsm_reset; 

reg [1:0] operation; 

 

reg is_valid; 

always@(posedge iValid or posedge iRST) begin 

if (iRST) begin 

is_valid<=0; 

end 

else begin  

if (fsm_reset==1) is_valid<=1; 

else if (fsm_reset==2)is_valid<=0; 

end 

end 

 

always @ (posedge iCLK or posedge iRST) 

begin  

if (iRST) begin 

oCounter<=0; 

fsm_reset<=1'b0; 

end  

else begin  

if (iStart) fsm_reset=1; 

else begin  

case(fsm_reset) 

0: begin 

oCounter<=0; 

fsm_reset<= 0; 

oEnable<=0; 

end 

1: begin  

if (is_valid) fsm_reset <=2; 

oEnable<=0; 

oCounter<=0; 

end  

2: begin 

if(oCounter<ADDRESS) begin 

oCounter<=oCounter+1; 

fsm_reset<=3; 

oEnable<=1; 

oData<=oCounter[7:0]; 

end 

else fsm_reset <= 0; 

end 

3: begin 

if(iDone)begin  

oEnable<=0; 

fsm_reset<=2; 

end 

end 

endcase 

end 

end 

end 

endmodule 

 

--- Quote End ---  

 

Ideally, it sohuld get signals from an WM8732 audio CODEC in master mode.  

iCLK is the AUD_BCLK, something around 3MHz. 

The state machine should start the [21 bits] count when I press a button and the signal iValid (left or right data channel) is high, to avoid a possible recordin in the middle of a high iValid state.  

iData is the "valid" data from the altera controller. If iData is low, the controller is still performing operations and the signal oEnable (that will be wired to a iWrite or iRead muxed by a switch) will stay high - untill iData goes low.  

In order to listen something, NOW data_out is internally generated by my function. 

Anyway, if I try to write (After erasing the flash) there is a whistle. If i am trying to perform a read, nothing. But if there are multiple reads, THEN there is the wishtle.  

Hints?
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