Assign DDR2 pins after creating a NIOS II project (DE2-530, QII V14, UniPHY)

[Altera_Forum]

The process of assigning pins can be a very hard task and specially if pseudo-differential buses (DQS and CK) are created. I was able to complete this task with success after several hour trying to solve this issue. 

Procedure: 1) After creating the NIOS II project as described in the DE4 user manual (pg. 128 to 131) include *.sdc and *.qip files to the project and define the *.qip as top entity. 2) run Analysis and Synthesis; 3) !VERY IMPORTANT! open the pin planer and manually assign the pins. 4) !VERY IMPORTANT! run the TCL script *_mem_if_ddr2_emif_p0_pin_assigments.tcl 5) Verify if the I/O standard SSTL-18 Class I is selected for the clock (if use the dedicated clock to bank 3) , ddr2_i2c_scl_* and ddr2_i2c_sda_*. 6) !VERY IMPORTANT! Delete the incremental_db folder inside the project folder. 7) Compile the project.  If the issue persists do the following procedure: 1) Open the Assignments Editor on the Assignments menu and leave only assignments related to pin location and I/O standard SSTL-18 Class I selection for the clock (if use the dedicated clock to bank 3) , ddr2_i2c_scl_* and ddr2_i2c_sda_* (check attached file) 2) run the TCL script *_mem_if_ddr2_emif_p0_pin_assigments.tcl  3) Delete the incremental_db folder inside the project folder. 4) Compile the project.  Drop me an e-mail if you have any further questions (pedrmachado@gmail.com). Regards, Pedro Machado

[Altera_Forum]

The full project can be found here https://drive.google.com/file/d/0b-v80y2dsbz2quntb3vfz01hmwm/view?usp=sharing. 

Details: Quartus II version: 14.0.0.200 Platform: Terasic DE4-530