Intel® FPGA University Program
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1129 Discussions

Audio Core IP with ST interface: Clock setting

Honored Contributor II

Hello everybody, this is my first Problem Report in this FORUM :D 



I'm trying to use the WOLFSON Audio CODEC on DE2 board to output an audio stream (96kSamples/sec) generated by Custom Hardware to the line-out port. 

As suggested by various University Program IP user guide Im using all the IPs needed: 


1) Clock Signals for DE-series Board Peripherals IP : with Audio clock exported to be connected to the audio chip (12.288Mhz- as suggested by datasheet) 

2) Audio and Video Configuration IP : set with (Auto-Initializa Device = 1; Audio_out = 1; Data_format = Left Justified ; Bit Lenght = 16; Sampling_Rate = 96kHz) 

3) Audio Core IP : set up with ST-interface , 16 bit-wide, and audio_out = 1; 


What should be the clock connection within this components? (Im sure that the fist IP need 2 clock inputs: 50Mhz and 27Mhz, but I've no idea about the Audio Core IP . The suggested datasheet is not clear about this point) 


Does the Audio and Video configuration IP set the CODEC in Master or Slave MODE?  

Does the Audio Core IP and the Audio CODEC use the same clock source?  


(i'm clearly configuring all the system on Qsys) 


I'm a bit confused about this point, the official documentation seems to have a lack on this aspect of interconnecting the audio University program IP. 


Best regards 



Thank you
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1 Reply
Honored Contributor II

Hello Lucazambuto, 

Your board is supplied with demo examples (cd or via  

You might want to take a look at them (DE2_115_Synthesizer). 

It is much easier to start from a working example then to build your application from scratch. 

Best Regards,