Intel® FPGA University Program
University Program Material, Education Boards, and Laboratory Exercises
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
1087 Discussions

Avalon interface for FIR filter

Honored Contributor II

Hi, my project is to design a 5-tap FIR filter. i have already completed the control unit,datapath unit, and also combined them. Now my task is to design an avalon interface for it. 


The problem is i dont know what should i do, and what is the need for the avalon interface :confused: 


Here i attached my codes, i really need some help in order to proceed........... 


0 Kudos
2 Replies
Honored Contributor II

Well I don't know either. You are suggesting that then asking us why you want to... 

Anyway from FIR perspective I assume an avalon IF will help to update coeffs if that is a requirement or to send input/receive output. 

So choose your task.
Honored Contributor II

does all the input and output for the cu/du top level need to be interfaced with the avalon IF? And what are things i need to write inside the verilog code? Thanks....