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Beginner
534 Views

Can you please help me out with the following problem:

i try to impliment this cod and ther is that Error (10822): HDL error at XOU.vhd(13): couldn't implement registers for assignments on this clock edge

library ieee; use ieee.std_logic_1164.all;     entity XOU is port (a,h,r,b:in std_logic;s:out std_logic); end XOU; architecture AXOU of XOU is begin process(h,r) begin if r='0' then s<='0'; elsif falling_edge(h)then s<='1'; else s<='0'; end if ;end process;end AXOU;

 

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Employee
27 Views

Hi,

just comment out the conflict line(-- else s<='0';)

 

Please let me know if you have any different concern.

Regards,

Vikas